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PDF IRUH3301A1AK Data sheet ( Hoja de datos )
| Número de pieza | IRUH3301A1AK | |
| Descripción | Radiation Hardended Ultra Low Dropout Adjustable Positive Linear Regulator | |
| Fabricantes | International Rectifier | |
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PD-97533A
IRUH3301A1AK
Radiation Hardended Ultra Low Dropout
IRUH3301A1AP
Adjustable Positive Linear Regulator +3.3VIN to VADJ @3.0A
Product Summary
Part Number
Dropout
IO
VIN VOUT
IRUH3301A1AK
IRUH3301A1AP
0.4V
3.0A
3.3V
ADJ
8-LEAD FLAT PACK
Description
Features
The IRUH3301A1 is a space qualified, ultra low dropout
linear regulator designed specifically for applications
requiring high reliability, low noise and radiation hardness.
The output voltage can be adjusted to a low 0.8V with a
droput voltage of 400mV at the full rated current of 3.0
Amps.
n Silicon On Insulator (SOI) CMOS Regulator
IC, CMOS Latch-Up Immune,
Inherently Rad Hard
n Total Dose Capability up to 300Krads(Si)
(Condition A); Tested to 500Krad (Si)
n ELDRS up to 100Krad(Si) (Condition D)
n SEU Immune up to LET = 80 MeV*cm2/mg
n Space Level Screened
n Fast Transient Response
Timed Latch-Off Over-Current Protectionhttp://www.DataSheet4U.net/
n
n Internal Thermal Protection
n Adjustable Output as low as 0.8V
n On/Off Control via Shutdown Pin, Power
Sequencing Easily Implemented
n Isolated Hermetic 8-Lead Flat Pack
Ensures Higher Reliability
n This part is also available in MO-078 Package
Absolute Maximum Ratings
as IRUH3301A1BK / IRUH3301A1BP
Parameter
Symbol
Min.
Max.
Units
Power Dissipation @ TC = 125°C
Maximum Output Current @ Maximum
Power Dissipation with no Derating
Non-Operating Input Voltage
Operating Input Voltage
Ground
Shutdown Pin Voltage
Output Pin Voltage
Operating Case Temperature Range
Storage Temperature Range
Maximmum Junction Temperature
Lead Temperature (Soldering 10sec)
Pass Transistor Thermal Resistance, Junction to Case
PD
IO
VIN
VIN
GND
VSHDN
VOUT
TO
TS
TJ
TL
RTHJC
- 25 W
-
See Fig 4
A
-0.3 +8.0
2.9 6.4
-0.3 0.3 V
-0.3 VIN + 0.3
-0.3 VIN + 0.3
-55 +140
-65
-
+150
+150
°C
- +300
- 1.0 °C/W
www.irf.com
1
08/02/10
datasheet pdf - http://www.DataSheet4U.net/
1 page  
IRUH3301A1AK
IRUH3301A1AP
Shutdown (SHDN)
The regulator can be shutdown by applying a voltage of >1.2V to the SHDN Pin. The regulator will
restart when the SHDN Pin is pulled below the shutdown threshold of 0.8V. If the remote shutdown
feature is not required, the SHDN Pin should be connected to GND.
Input Capacitance
Input bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX
TPS or equivalent), placed very close to the VIN Pin are required for proper operation. When the
input voltage supply capacitance is more than 4 inches from the device, additional input
capacitance is recommended. Larger input capacitor values will improve ripple rejection further
improving the integrity of the output voltage.
Output Capacitance
Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums
(AVX TPS or equivalent) are required for loop stability. Faster transient performance can be
achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in
value are not recommended as they can cause stability issues.
Tantalum capacitor values larger than the suggested value are recommended to improve the
transient response under large load current changes. The upper capacitance value limit is
governed by the delayed over-current latch function of the regulator and can be as much as
10,000µF without causing the device to latch-off during start-up.
General Layout Rules
Low impedance connections between the regulator output and load are essential. Solid power and
ground planes are highly recommended. In those caseshttp://www.DataSheet4U.net/ where the board impedances are not kept
very small, oscillations can occur due to the effect of parasitic series resistance and inductance
on loop bandwidth and phase margin.
R1 must be directly conected to the VOUT Pin using as short a trace as possible with the
connection inside the first bypass capacitor (see Fig. 2a). The trace from ADJ Pin to R1 should
be as short as possible.
Connect ceramic output capacitors directly across the VOUT and GND Pins with as wide a trace as
design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2
shows the ceramic capacitors tied directly to the regulator output.
The input capacitors should be connected as close a possible to the VIN Pin.
Fig. 2a. Layer 1 conductor.
Ground plane below layer 1
www.irf.com
Fig. 2b. Layer 1 silkscreen
5
datasheet pdf - http://www.DataSheet4U.net/
5 Page | ||
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