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PDF HT48R05A-1 Data sheet ( Hoja de datos )
| Número de pieza | HT48R05A-1 | |
| Descripción | Cost-Effective I/O Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT48R05A-1/HT48C05/
HT48R06A-1/HT48C06/HT48R08A-1
Cost-Effective I/O Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0013E HT48 & HT46 LCM Interface Design
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0049E Read and Write Control of the HT1380
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 13 bidirectional I/O lines
· An interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with over-
flow interrupt and 8-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· Program memory ROM:
512´14 for HT48R05A-1/HT48C05
1024´14 for HT48R06A-1/HT48C06
2048´14 for HT48R08A-1
· Data memory RAM
32´8 for HT48R05A-1/HT48C05
64´8 for HT48R06A-1/HT48C06
96´8 for HT48R08A-1
· Buzzer driving pair and PFD supported
· HALT function and wake-up feature reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Allinstructionsinoneortwomachinecycles
· 14-bit table read instruction
· Two-level subroutine nesting
· Bit manipulation instruction
· Powerful instructions:
62 for HT48R05A-1/HT48C05
63 for HT48R06A-1/HT48C06 and HT48R08A-1
· Low voltage reset function
· 16-pin SSOP/NSOP package
www.DataSheet.net/
18-pin DIP/SOP package
General Description
The HT48R05A-1/HT48C05, HT48R06A-1/HT48C06
and HT48R08A-1 are 8-bit high performance, RISC ar-
chitecture microcontroller devices specifically designed
for cost-effective multiple I/O control product applica-
tions. The mask version HT48C05 and HT48C06 are
fully pin and functionally compatible with the OTP ver-
sion HT48R05A-1 and HT48R06A-1 devices.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, Watchdog Timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Selection Table
Part No.
VDD
Program Data
Memory Memory
I/O
HT48R05A-1
HT48C05
2.2V~5.5V
0.5K´14
HT48R06A-1
HT48C06
2.2V~5.5V
1K´14
32´8
64´8
13
13
Timer
8-bit´1
8-bit´1
HT48R08A-1 2.2V~5.5V 2K´14 96´8 13 8-bit´1
Int.
2
2
2
PFD
Ö
Ö
Ö
Stack
2
2
2
Package
Types
16SSOP/NSOP,
18DIP/SOP
16SSOP/NSOP,
18DIP/SOP
16SSOP/NSOP,
18DIP/SOP
Rev. 1.51
1 December 30, 2008
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06/HT48R08A-1
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are exe-
cuted and its contents specify full range of program
memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T1 T2 T3 T4 T1
S y s te m C lo c k
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T2 T3 T4 T1 T2 T3 T4
O S C 2 ( R C o n ly )
PC PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
www.DataSheet.net/
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset
00000000000
External Interrupt
00000000100
Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 0 0 0
Skip
Program Counter+2
Loading PCL
*10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
#10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: *10~*0: Program Counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
@7~@0: PCL bits
For HT48R05A-1/HT48C05, the Program Counter is 9 bits wide, i.e. from *8~*0
For HT48R06A-1/HT48C06, the Program Counter is 10 bits wide, i.e. from *9~*0
For HT48R08A-1, the Program Counter is 11 bits wide, i.e. from *10~*0
Rev. 1.51
5 December 30, 2008
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06/HT48R08A-1
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the ²CLR WDT² instruction and is set when execut-
ing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the Program Counter and SP; the others keep their orig-
inal status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset Timing Chart
V DD V DD
0 .0 1 m F
100kW
0 .1 m F
RES
B a s ic
R eset
C ir c u it
100kW
10kW
0 .1 m F
RES
H i-n o is e
R eset
C ir c u it
Reset Circuit
Note:
Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H A LT
W DT
W a rm R e s e t
RES
O SC1
SST
1 0 - b it R ip p le
C o u n te r
C o ld
R eset
www.DataSheet.net/
S y s te m R e s e t
Reset Configuration
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Rev. 1.51
11 December 30, 2008
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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