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AD9557 の電気的特性と機能

AD9557のメーカーはAnalog Devicesです、この部品の機能は「Dual Input Multiservice Line Card Adaptive Clock Translator」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9557
部品説明 Dual Input Multiservice Line Card Adaptive Clock Translator
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9557 Datasheet, AD9557 PDF,ピン配置, 機能
Data Sheet
Dual Input Multiservice
Line Card Adaptive Clock Translator
AD9557
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually
no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
2 reference inputs (single-ended or differential)
Input reference frequencies: 2 kHz to 1250 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as
a single differential LVDS/HSTL output or as 2 single-ended
CMOS outputs
Output frequencies: 360 kHz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional
feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths
from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking)
Low noise system clock multiplier
Frame sync support
Adaptive clocking
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation
configuration
Software controlled power-down
40-lead, 6 mm × 6 mm, LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and SDH to OTN mapping/demapping
Cleanup of reference clock jitter
SONET/SDH/OTN clocks up to 100 Gbps, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient control
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9557 is a low loop bandwidth clock multiplier that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (OTN/SONET/SDH).
The AD9557 generates an output clock synchronized to up to
four external input references. The digital PLL allows for
reduction of input time jitter or phase noise associated with
the external references. The digitally controlled loop and
holdover circuitry of the AD9557 continuously generates a low
jitter output clock even when all reference inputs have failed.
The AD9557 operates over an industrial temperature range
of −40°C to +85°C. If more inputs/outputs are needed, refer to
the AD9558 for the four-input/six-output version of the same
device.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE INPUT
AND
MONITOR MUX
AD9557
DIGITAL
PLL
ANALOG
PLL
÷3 TO ÷11
HF DIVIDER 0
÷3 TO ÷11
HF DIVIDER 1
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CLOCK
MULTIPLIER
SERIAL INTERFACE
(SPI OR I2C)
EEPROM
STATUS AND
CONTROL PINS
STABLE
SOURCE
Figure 1.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





AD9557 pdf, ピン配列
AD9557
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Loop Control State Machine..................................................... 34
Applications....................................................................................... 1
System Clock (SYSCLK)................................................................ 35
General Description ......................................................................... 1
System Clock Inputs................................................................... 35
Functional Block Diagram .............................................................. 1
SYStem Clock Multiplier ........................................................... 35
Revision History ............................................................................... 3
Output PLL (APLL) ....................................................................... 37
Specifications..................................................................................... 5
Clock Distribution.......................................................................... 38
Supply Voltage............................................................................... 5
Output Power-Down ................................................................. 38
Supply Current.............................................................................. 5
Output Enable............................................................................. 38
Power Dissipation......................................................................... 6
Output Mode .............................................................................. 38
Logic Inputs (RESET, SYNC, PINCONTROL, M3 to M0) .... 6
Clock Distribution Synchronization........................................ 38
Logic Outputs (M3 to M0, IRQ) ................................................ 7
Status and Control.......................................................................... 40
System Clock Inputs (XOA, XOB) ............................................. 7
Multifunction Pins (M3 to M0) ............................................... 40
Reference Inputs ........................................................................... 8
IRQ Pin ........................................................................................ 40
Reference Monitors ...................................................................... 9
Watchdog Timer......................................................................... 41
Reference Switchover Specifications.......................................... 9
EEPROM ..................................................................................... 41
Distribution Clock Outputs ...................................................... 10
Serial Control Port ......................................................................... 47
Time Duration of Digital Functions ........................................ 11
SPI/I²C Port Selection................................................................ 47
Digital PLL .................................................................................. 12
SPI Serial Port Operation .......................................................... 47
Digital PLL Lock Detection ...................................................... 12
I2C Serial Port Operation .......................................................... 51
Holdover Specifications............................................................. 12
Programming the I/O Registers ................................................... 54
Serial Port Specifications—SPI Mode...................................... 13
Buffered/Active Registers.......................................................... 54
Serial Port Specifications—I2C Mode ...................................... 14
Autoclear Registers..................................................................... 54
Jitter Generation ......................................................................... 14
Register Access Restrictions...................................................... 54
Absolute Maximum Ratings.......................................................... 17
Thermal Performance.................................................................... 55
ESD Caution................................................................................ 17
Power Supply Partitions................................................................. 56
Pin Configuration and Function Descriptions........................... 18
Recommended Configuration for 3.3 V Switching Supply..... 56
Typical Performance Characteristics ........................................... 20
Configuration for 1.8 V Supply ................................................ 56
Input/Output Termination Recommendations .......................... 25
Pin Program Function Description ............................................. 57
Getting Started ................................................................................ 26
Overview of On-Chip ROM Features ..................................... 57
Chip Power Monitor and Startup............................................. 26
Hard Pin Programming Mode.................................................. 58
Multifunction Pins at Reset/Power-Up ................................... 26
Soft Pin Programming Mode Overview ................................. 58
Device Register Programming Using a Register Setup File .....26
Register Map ................................................................................... 59
Register Programming Overview............................................. 27
Register Map Bit Descriptions ...................................................... 68
Theory of Operation ...................................................................... 30
Overview...................................................................................... 30
Reference Clock Inputs.............................................................. 31
Reference Monitors .................................................................... 31
Reference Profiles ....................................................................... 31
Reference Switchover ................................................................. 31
Digital PLL (DPLL) Core .......................................................... 32
Serial Port Configuration (Register 0x0000 to
Register 0x0005) ......................................................................... 68
Silicon Revision (Register 0x000A) ......................................... 68
Clock Part Serial ID (Register 0x000C to
Register 0x000D) ........................................................................ 68
System Clock (Register 0x0100 to Register 0x0108) ............. 69
General Configuration (Register 0x0200 to
Register 0x0214) ......................................................................... 70
Rev. C | Page 2 of 95


3Pages


AD9557 電子部品, 半導体
Data Sheet
AD9557
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA = 25°C, unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD3
DVDD
AVDD3
AVDD
Min Typ Max Unit Test Conditions/Comments
3.135 3.30 3.465 V
1.71 1.80 1.89 V
3.135 3.30 3.465 V
1.71 1.80 1.89 V
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3.
The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3.
Table 2.
Parameter
SUPPLY CURRENT FOR TYPICAL
CONFIGURATION
IDVDD3
IDVDD
IAVDD3
IAVDD
SUPPLY CURRENT FOR THE ALL BLOCKS
RUNNING CONFIGURATION
IDVDD3
IDVDD
IAVDD3
IAVDD
Min
12
13
35
112
12
10
47
113
Typ Max Unit Test Conditions/Comments
Typical numbers are for the typical configuration listed
in Table 3
18 26 mA Pin 30, Pin 31, Pin 40
20 28 mA Pin 6, Pin 34, Pin 35
49 63 mA Pin 14, Pin 19
162 215 mA Pin 7, Pin 10, Pin 11, Pin 17, Pin 18, Pin 22, Pin 23, Pin 24
Maximum numbers are for all blocks running configuration
in Table 3
18 33 mA Pin 30, Pin 31, Pin 40
19 30 mA Pin 6, Pin 34, Pin 35
68 89 mA Pin 14, Pin 19
163 215 mA Pin 7, Pin 10, Pin 11, Pin 17, Pin 18, Pin 22, Pin 23, Pin 24
Rev. C | Page 5 of 95

6 Page



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