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PDF SiM3L157-C-GL Data sheet ( Hoja de datos )
| Número de pieza | SiM3L157-C-GL | |
| Descripción | MCU | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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SiM3L1xx
High-Performance, Low-Power, 32-Bit Precision32™
MCU Family with up to 256 kB of Flash
32-bit ARM Cortex-M3 CPU
- 50 MHz maximum frequency
- Single-cycle multiplication, hardware division support
- Nested vectored interrupt control (NVIC) with 8 priority levels
Memory
- 32–256 kB flash, in-system programmable
- 8–32 kB SRAM with configurable low power retention
Clock Sources
- Internal oscillator with PLL: 23–50 MHz
- Low power internal oscillator: 20 MHz
- Low frequency internal oscillator (LFO): 16.4 kHz
- External real-time clock (RTC) crystal oscillator
- External oscillator: Crystal, RC, C, CMOS clock
Power Management
- Three adjustable low drop-out (LDO) regulators
- Power-on reset circuit and brownout detectors
- DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
- Multiple power modes supported for low power optimization
Low Power Features
- 50 nA current mode with voltage supply monitor enabled
- Low-current RTC (180 nA from LFO, 300 nA from crystal)
- 4 µs wakeup, register state retention and no reset required from
lowest power mode
- 175 µA/MHz at 3.6 V executing from flash
- 140 µA/MHz at 3.6 V executing from SRAM
- Specialized on-chip charge pump reduces power consumption
- Process/Voltage/Temperature (PVT) Monitor
5 V Tolerant Flexible I/O
- Up to 62 contiguous 5 V tolerant GPIO with one priority cross-
bar providing flexibility in pin assignments
Temperature Range: –40 to +85 °C
Supply Voltage: 1.8 to 3.8 V
Analog Peripherals
- 12-Bit Analog-to-Digital Converter: Up to 250 ksps 12-bit mode
or 1 Msps 10-bit mode
- 10-Bit Current-mode Digital-to-Analog Converter
- 2 x Low-current comparators
Digital and Communication Peripherals
- 1 x USART with IrDA and ISO7816 Smartcard support
- 1 x UART that operates in low power mode
- 2 x SPIs, 1 x I2C, 16/32-bit CRC
- 128/192/256-bit Hardware AES Encryption
- Encoder/Decoder: Manchester and Three-out-ofSix
- Integrated LCD Controller: up to 160 segments (40x4), auto-
contrast and low power operation
Timers/Counters
- 3 x 32-bit or 6 x 16-bit timers with capture/compare
- 16-bit, 6-channel counter with capture/compare/PWM and
dead-time controller with differential outputs
- 16-bit low power timer/advanced capture counter operational in
the lowest power mode
- 32-bit real time clock (RTC) with multiple alarms
- Watchdog timer
- Low power mode advanced capture counter (ACCTR)
Data Transfer Peripherals
- 10-Channel DMA Controller
- 3 Channel Data Transfer Manager manages complex DMA
transferswww.DataSheet.net/ without core intervention
On-Chip Debugging
- Serial wire debug (SWD) with serial wire viewer (SWV) or JTAG
(no boundary scan) allow debug and programming
- Cortex-M3 embedded trace macrocell (ETM)
Package Options
- QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)
- TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)
- TFBGA option: 80-ball (5.5 x 5.5 mm)
Power
Scalable Digital LDO
Scalable Memory LDO
Scalable Analog LDO
DC-DC Buck Converter
Low Power Mode Charge Pump
Power Management Unit
Core / Memory / Support
ARM Cortex M3 (50 MHz)
32/64/128/256 kB Flash
8/16/32 kB Retention
RAM
10-Ch DMA Controller + 3x Data Transfer Mgr.
Watchdog
Supply Monitor
Serial Wire or JTAG Debug / Programming + ETM
Analog Peripherals
SAR ADC
(12-bit 250 ksps / 10-bit 1 Msps)
Voltage Reference
Current-Source DAC
2 x Low Current Comparators
Advanced Capture Counter
Clocking / Oscillators
50 MHz PLL
Real-Time Clock w/ Dedicated Crystal Oscillator
16 kHz Low Frequency Oscillator
20 MHz Low Power Oscillator
External Clock (XTAL / RC / C / CMOS)
Digital Peripherals
1 x I2C
2 x SPI
AES
CRC
3 x 32-bit Timers (6 x 16-bit)
1 x UART, 1 x USART w/ IrDA/SmartCard
Encoder/Decoder
Low-Power Timer
6-Channel PWM
LCD Controller
Rev 0.4 9/12
Copyright © 2012 by Silicon Laboratories
SiM3L1xx
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
SiM3L1xx
1. Related Documents and Conventions
1.1. Related Documents
This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices.
1.1.1. SiM3L1xx Reference Manual
The Silicon Laboratories SiM3Lxxx Reference Manual provides the detailed description for each peripheral on the
SiM3L1xx devices.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read
each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found here:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Internal Module
Other Internal
Peripheral Block
DMA Block
External Memory
Block
www.DataSheet.net/
Memory Block
External to MCU
Block
Input_Pin
Internal_Input_Signal
Functional Block
REGn_NAME / BIT_NAME
Figure 1.1. Block Diagram Conventions
Output_Pin
Internal_Output_Signal
Rev 0.4
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
SiM3L1xx
Table 3.2. Power Consumption (Continued)
Parameter
Symbol
Condition
Min Typ Max Unit
Power Mode 41,2,4,5—Slower clock
speed with code executing from
flash, peripheral clocks ON
IBAT
Power Mode 51,2,4,5—Slower clock
speed with code executing from
RAM, peripheral clocks ON
IBAT
Power Mode 61,2,4,5—Core halted
with peripheral clocks ON
IBAT
FAHB = FAPB = 16 kHz,
VBAT = 1.8 V
FAHB = FAPB = 16 kHz,
VBAT = 3.8 V
FAHB = FAPB = 16 kHz,
VBAT = 1.8 V
FAHB = FAPB = 16 kHz,
VBAT = 3.8 V
FAHB = FAPB = 16 kHz,
VBAT = 1.8 V
— 330 TBD µA
— 385 TBD µA
— 275 TBD µA
— 320 TBD µA
— 270 TBD µA
Power Mode 81,2—Low Power
Sleep, powered through VBAT,
VIO, and VIORF at 2.4 V, 32kB of
retention RAM
IBAT
FAHB = FAPB = 16 kHz,
VBAT = 3.8 V
RTC Disabled,
TA = 25 °C
RTC w/ 16.4 kHz LFO,
TA = 25 °C
— 315 TBD µA
— 75 TBD nA
— 360 TBD nA
RTC w/ 32.768 kHz Crystal, — 670 TBD nA
TA = 25 °C
Power Mode 81,2—Low Power
IBAT RTC w/ 16.4 kHz LFO, — 180 TBD nA
Sleep, powered by the low power
VBAT = 2.4 V, TA = 25 °Cwww.DataSheet.net/
mode charge pump, 32kB of reten-
tion RAM
RTC w/ 32.768 kHz Crystal, — 300 TBD nA
VBAT = 2.4 V, TA = 25 °C
RTC w/ 16.4 kHz LFO,
VBAT = 3.6 V, TA = 25 °C
— 245 TBD nA
RTC w/ 32.768 kHz Crystal, — 390 TBD nA
VBAT = 3.6 V, TA = 25 °C
Power Mode 8 Peripheral Currents
UART0
IUART0
VBAT = 2.4 V, TA = 25 °C
— 120 TBD nA
LCD06, No segments active
ILCD0
VBAT = 3.8 V, TA = 25 °C
VBAT = 2.4 V, TA = 25 °C
— 195 TBD nA
— 395 TBD nA
VBAT = 3.8 V, TA = 25 °C
— 495 TBD nA
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Includes LFO supply current.
6. LCD0 current does not include switching currents for external load.
7. IDAC output current not included.
8. Does not include LC tank circuit.
Rev 0.4
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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