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843252AGLF の電気的特性と機能

843252AGLFのメーカーはIntegrated Circuit Systemです、この部品の機能は「 ICS843252AGLF」です。


製品の詳細 ( Datasheet PDF )

部品番号 843252AGLF
部品説明 ICS843252AGLF
メーカ Integrated Circuit System
ロゴ Integrated Circuit System ロゴ 




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843252AGLF Datasheet, 843252AGLF PDF,ピン配置, 機能
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843252
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843252 is a 2 differential output LVPECL
ICS Synthesizer designed to generate Ethernet refer-
HiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequen-
cies can be generated based on the settings of 4 frequency
select pins (SEL[A1:A0], SEL[B1:B0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz.
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies
mentioned above. The ICS843252 ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS843252 is packaged in a small
16-pin TSSOP package.
FEATURES
• Two 3.3V differential LVPECL output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Crystal oscillator interface
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.47ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard and lead-free RoHS-compliant
packages
www.DataSheet.co.kr
BLOCK DIAGRAM
SELA[0:1} Pullup
2
XTAL_IN
XTAL_OUT
OSC
Phase
Detector
VCO
490MHz - 680MHz
FB_SEL Pulldown
SELB[0:1} Pullup
2
Feedback Divider
0 = ÷25 (default)
1 = ÷32
0 0 ÷1
0 1 ÷2
1 0 ÷3
1 1 ÷4 (default)
0 0 ÷2
0 1 ÷4
1 0 ÷5
1 1 ÷8 (default)
QA
nQA
QB
nQB
PIN ASSIGNMENT
nQB
QB
VCCO_B
SELB1
SELB0
VCCO_A
QA
nQA
1
2
3
4
5
6
7
8
16 XTAL_IN
15 XTAL_OUT
14 VEE
13 SELA1
12 SELA0
11 VCC
10 VCCA
9 FB_SEL
ICS843252
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843252AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 9, 2005
1
Datasheet pdf - http://www.DataSheet4U.net/

1 Page





843252AGLF pdf, ピン配列
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843252
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 3A. BANK A FREQUENCY TABLE
Inputs
Crystal Frequency
(MHz)
25
25
20
22.5
25
24
20
19.44
19.44
15.625
18.75
19.44
18.75
15.625
FB_SEL
0
0
0
0
0
0
0
1
1
1
1
1
1
1
SELA1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
SELA0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
Feedback
Divider
Bank A
Output Divider
M/N
Multiplication
Factor
25 1
25
25 2
12.5
25 2 12.500
25 3 8.333
25 4
6.25
25 4
6.25
25 4
6.25
32 1
32
32 2
16
32 2
16
32 3 10.667
32 4
8
32 4
8
32 4
8
QA/nQA
Output
Frequency
(MHz)
625
312.5
250
187.5
156.25
150
125
622.08
311.04
250
200
155.52
150
125
www.DataSheet.co.kr
843252AG
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 9, 2005
Datasheet pdf - http://www.DataSheet4U.net/


3Pages


843252AGLF 電子部品, 半導体
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843252
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
FB_SEL = ÷25
FB_SEL = ÷32
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
19.6 27.2
15.313
21.25
50
7
1
Units
MHz
MHz
Ω
pF
mW
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Output Divider = ÷1
490
Output Divider = ÷2
245
fOUT Output Frequency Range
Output Divider = ÷3
Output Divider = ÷4
163.33
122.5
Output Divider = ÷5
98
Output Divider = ÷8
61.25
tsk(o) Output Skew; NOTE 1, 3
Outputs @ Same Frequency
www.DataSheet.co.kr
Outputs @ Different Frequencies
TBD
TBD
625MHz (1.875MHz - 20MHz)
0.36
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
312.5MHz (1.875MHz - 20MHz)
156.25MHz (1.875MHz - 20MHz)
0.43
0.47
125MHz (1.875MHz - 20MHz)
0.47
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
350
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
680
340
226.67
170
136
85
Units
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
843252AG
www.icst.com/products/hiperclocks.html
6
REV. A NOVEMBER 9, 2005
Datasheet pdf - http://www.DataSheet4U.net/

6 Page



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部品番号部品説明メーカ
843252AGLF

ICS843252AGLF

Integrated Circuit System
Integrated Circuit System


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