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ISL97687 の電気的特性と機能

ISL97687のメーカーはIntersilです、この部品の機能は「4-Channel LED Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL97687
部品説明 4-Channel LED Driver
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL97687 Datasheet, ISL97687 PDF,ピン配置, 機能
4-Channel LED Driver with Phase Shift Control and
10-Bit Dimming Resolution
ISL97687
The ISL97687 is a PWM controlled LED driver that supports
4 channels of LED current, for Monitor and TV LCD backlight
applications. It is capable of driving 160mA per channel from a
9V to 32V input supply, with current sources rated up to 75V
absolute maximum.
The ISL97687’s current sources achieve typical current matching
to ±1%, while dynamically maintaining the minimum required
VOUT necessary for regulation. This adaptive scheme
compensates for the non-uniformity of forward voltage variance
in the LED strings.
The ISL97687 can decode both an incoming PWM signal and an
analog input voltage, for DC-to-PWM dimming applications.
Modes include direct PWM and several modes where the PWM
frequency is synthesized on chip at 10-bit resolution. This can be
either free running, or synchronized with the frame rate to give
both a frequency and a phase lock, minimizing panel to panel
variation and display flicker. Phase shift is supported, reducing
flicker and audio noise, as is multiplication of the incoming
decoded analog and PWM values.
The ISL97687 has an advanced dynamic headroom control
function, which monitors the highest LED forward voltage string,
and regulates the output to the correct level to minimize power
loss. This proprietary regulation scheme also allows for
extremely linear PWM dimming from 0.02% to 100%. The LED
current can also be switched between two current levels, giving
support for 3D applications. The ISL97687 incorporates
extensive protections of string open and short circuit detections,
OVP, and OTP.
Features
• 4x160mA, 75V Rated Channels with Integrated Channel
Regulation FETs
• Channels can be Ganged for High Current
- 2x350mA
- 1x700mA
• 9V~32V Input Voltage
• Dimming Modes:
- Direct PWM Dimming from 100Hz~30kHz
- PWM Dimming with Adjustable Output Frequency
- 10-bit Dimming Resolution
- VSYNC Function to Synchronize PWM Signal to Frame Rate
- Phase Shift
- Analog to PWM Dimming with 8-bit Resolution
• 2 Selectable Current Levels for 3D Applications
• Current Matching of ±1%
• Integrated Fault Protection Features such as String Open
Circuit Protection, String Short Circuit Protection, Overvoltage
Protection, and Over-Temperature Protection
• 28 Ld 5x5mm TQFN and 28 Ld 300mil SOIC Packages Available
Applicationswww.DataSheet.co.kr
• Monitor/TV LED Backlighting
• General/Industrial/Automotive Lighting
Related Literature
• See Apnote for “ISL97687IRTZ_LEVALZ” or
“ISL97687IRTZ_HEVALZ” for TQFN Application
• See Apnote for “ISL97687IBZ-EVAL1Z” for SOIC Application
VIN: 9V~32V
FUSE
VIN
VDC
VLOGIC
EN
STV
EN_VSYNC
EN_ADIM
PWMI
ACTL
EN_PS
SLEW
GD
CS
PGND
COMP
OVP
CSEL
ISET1
ISET2
OSC
PWM_SET/PLL
CH1
CH2
CH3
CH4
D1 160mA MAX PER STRING
Q1
RSENSE
FIGURE 1. ISL97687 APPLICATION DIAGRAM
110
100
90
80
70
60
50
40
30
20
10
0
0
I_CH2
I_CH3
I_CH1
I_CH4
20 40 60 80
DIMMING DUTY CYCLE (%)
FIGURE 2. PWM DIMMING LINEARITY
100
September 15, 2011
FN7714.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/

1 Page





ISL97687 pdf, ピン配列
Pin Configurations
ISL97687
(28 LD 5x5 TQFN)
TOP VIEW
ISL97687
PWMI 1
28 27 26 25 24 23 22
21 ACTL
STV 2
20 OSC
EN_ADIM 3
EN_PS 4
VLOGIC 5
THERMAL*
PAD
19 ISET2
18 ISET1
17 COMP
EN_VSYNC 6
16 OVP
VDC 7
15 PWM_SET/PLL
8 9 10 11 12 13 14
*EXPOSED THERMAL PAD
CH2 1
CH1 2
PGND 3
CSEL 4
PWMI 5
STV 6
EN_ADIM 7
EN_PS 8
VLOGIC 9
EN_VSYNC 10
VDC 11
VIN 12
EN 13
AGND 14
ISL97687
(28 LD SOIC)
TOP VIEW
28 CH3
27 CH4
26 PGND
25 ACTL
24 OSC
23 ISET2
22 ISET1
21 COMP
20 OVP
19 PWM_SET/PLL
18 PGND
17 CS
16 SLEW
15 GD
Pin Descriptions
TQFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SOIC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PIN NAME PIN TYPE
www.DataSheet.co.kr
PIN DESCRIPTION
PWMI
I PWM Brightness Control Input pin
STV I Start Vertical Frame signal, used in VSYNC mode
EN_ADIM
I Enable Analog Dimming
EN_PS
I Enable Phase Shift
VLOGIC
S Internal 2.5V Digital Bias Regulator. Needs Decoupling Capacitor added to ground
EN_VSYNC
I Frame synchronization enable. Ties high to VDC for enable VSYNC function. PWM_SET/PLL also
needs to be configured with an RC network. Pin can be tied to VDC or VLOGIC to enable function
VDC S Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor added ground
VIN S Main Power Input. Range: 9V to 32V
EN I LED Driver Enable. Whole chip will shut down when low
AGND
S Analog Ground
GD O External Boost FET gate control
SLEW
I Boost Regulation Switching Slew Rate control
CS I External Boost FET current sense input
PGND
S Boost FET gate driver power ground and ground reference for CS pin
PWM_SET/ I For direct PWM mode, tie this pin high to VDC. For other non-VSYNC modes, connect to a resistor
PLL to set the dimming frequency. If the VSYNC function is enabled, connect this pin to the PLL loop
filter network.
OVP I Overvoltage Protection Input as well as Output Voltage feedback pin
COMP
I Boost compensation
3 FN7714.0
September 15, 2011
Datasheet pdf - http://www.DataSheet4U.net/


3Pages


ISL97687 電子部品, 半導体
ISL97687
Absolute Maximum Ratings (TA = +25°C)
VIN, EN, PWMI, ACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
VDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
COMP, ISET1, ISET2, PWM_SET,
OSC, CS, OVP. . . . . . . . . . . . . . . . . . . . . . .-0.3V to min (VDC+0.3V, 5.75V)
EN_VSYNC, CSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
STV, EN_ADIM, EN_PS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
CH1 - CH4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 75V
GD, SLEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (JESD22-C101E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
28 Ld TQFN (4 layer + vias, Notes 4, 5) . . .
32
4
28 Ld SOIC (4 layer, Notes 4, 6) . . . . . . . . .
54
25
Thermal Characterization (Typical, Note 7)
PSIJT (°C/W)
28 Ld TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
28 Ld SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation
TQFN (W) SOIC (W)
TA < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13
1.85
TA < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.72
1.02
TA < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25
0.74
TA < +105°C . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.63
0.37
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. For θJC, the “case temp” location is taken at the package top center.
7. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the θJC and θJC thermal resistance ratings.
Electrical Specifications All
specifications
below
are
characterized
www.DataSheet.co.kr
at
TA
=
-40°C
to
+105°C;
VIN
=
12V,
EN
=
5V.
Boldface
limits
apply
over the operating temperature range, -40°C to +105°C.
PARAMETER
DESCRIPTION
CONDITION
MIN MAX
(Note 8) TYP (Note 8) UNIT
GENERAL
VIN
IVIN_STBY
IVIN_ACTIVE
Backlight Supply Voltage
VIN Shutdown Current
Switching
Non-switching
(Note 9)
EN = 0
RFPWM = 3.3k,
ILED = 100mA,
fSW = 600kHz,
COUT_SW = 1nF
9 32 V
5 µA
10 13 mA
4 5.5 mA
VUVLO
Undervoltage Lock-out Threshold
VUVLO_HYS
Undervoltage Lock-out Hysteresis
LINEAR REGULATOR
2.9 3.3 V
300 mV
VDC 5V Analog Bias Regulator
VDC_DROP
VDC LDO Load Regulation Tolerance
VLOGIC
2.5V Logic Bias Regulator
VLOGIC_DROP
VLOGIC LDO Load Regulation Tolerance
BOOST SWITCH CONTROLLER
VIN > 6V
IVDC = 30mA
VIN > 6V
IVLOGIC = 30mA
4.8 5 5.1 V
71 100 mV
2.3 2.4 2.5 V
31 100 mV
tSS
ISW_LIMIT
tR
tF
Soft-Start
Boost FET Current Limit
Gate Rise Time
Gate Falling Time
RSENSE = 50m
COUT_SW = 1000pF
COUT_SW = 1000pF
16 ms
3.1 3.4 3.8 A
20 ns
17.6 ns
6 FN7714.0
September 15, 2011
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6 Page



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