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PDF ISL98003 Data sheet ( Hoja de datos )
| Número de pieza | ISL98003 | |
| Descripción | 8-Bit Video Analog Front End | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
September 25, 2008
ISL98003
FN6760.0
8-Bit Video Analog Front End (AFE) with
Measurement and Auto-Adjust Features
The ISL98003 3-channel, 8-bit Analog Front End (AFE)
contains all the functionality needed to digitize analog YPbPr
video from HDTV tuners, set-top boxes, SD and HD DVDs,
as well as RGB graphics signals from personal computers
and workstations. The fourth generation analog design
delivers 8-bit performance and a 165MSPS maximum
conversion rate supporting resolutions up to UXGA at 60Hz.
The front end's programmable input bandwidth ensures
sharp, low noise images at all resolutions.
To accelerate and simplify mode detection, the ISL98003
integrates a sophisticated set of measurement tools that fully
characterizes the video signal and timing, offloading the host
microcontroller. Automatic Black Level Compensation
(ABLC™) eliminates part-to-part offset variation, ensuring
perfect black level performance in every application.
The ISL98003's Digital PLL generates a pixel clock from the
analog source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 165MHz
with sampling clock jitter of 250ps peak-to-peak.
Applications
• Flat Panel TVs
• Front/Rear Projection TVs
• PC LCD Monitors and Projectors
• High Quality Scan Converters
• Video/Graphics Processing
Simplified Block Diagram
Features
• 8-Bit Triple Analog-to-Digital Converters with
Oversampling Up to 8x in Video Modes
• Fast Automatic Selection of Best Sampling Phase
• 165MSPS Maximum Conversion Rate
(ISL98003CNZ-165)
• Robust, Glitchless Macrovision™-Compliant Sync
Separator
• Analog VCR “Trick Mode” Support
• ABLC for Perfect Black Level Performance
• 2-Channel Input Multiplexer
• Precision Sync Timing Measurement
• RGB to YUV Color Space Converter
• Low PLL Clock Jitter (250ps Peak-to-Peak)
• Programmable Input Bandwidth (10MHz to 450MHz)
• 64 Interpixel Sampling Positions
• ±6dB Gain Adjustment Range
• Pb-Free (RoHS compliant)
Related Literaturewww.DataSheet.co.kr
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”.
RGB/YPbPrIN0
RGB/YPbPrIN1
3
3
SOGIN0, 1
HSYNCIN0, 1
VSYNCIN0, 1
VOLTAGE
CLAMP
OFFSET
DAC
ABLC™
PGA
+
8-BIT ADC
SYNC
PROCESSING
DIGITAL PLL
COLOR SPACE 8
CONVERTER X3
RGB/YUVOUT
2 H/VSYNCOUT
FIELDOUT
DEOUT
HSOUT
PIXELCLKOUT
MEASUREMENT, AUTOADJUST, AFE CONFIGURATION AND CONTROL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
ISL98003
Electrical Specifications
Specifications apply for VA3.3 = VD3.3 = VPLLA3.3 = 3.3V, VA1.8 = VD1.8 = VPLLD1.8 = VADCD1.8 = 1.8V,
pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165,
fXTAL = 25MHz, and TA = +25°C, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST LEVEL or NOTES
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
VA1.8
VD3.3
VD1.8
IA3.3
Analog Supply Voltage, 1.8V
Digital Supply Voltage, 3.3V
Digital Supply Voltage, 1.8V
Analog Supply Current, 3.3V
(Note 4)
Includes VADCD1.8, VPLLD1.8
1.65 1.8
3.0 3.3
1.65 1.8
40
2.0 V
3.6 V
2.0 V
90 mA
IPLLA3.3
IA1.8
Analog Supply Current, 1.8V
(Note 4)
Includes 1.8V ADC reference current
draw
14 25 mA
280 375 mA
ID3.3
Digital Supply Current, 3.3V
(Note 4)
Grayscale ramp input
40 60 mA
ID1.8
IADCD1.8
IPLLD1.8
PD
Digital Supply Current, 1.8V
(Note 4)
Total Power Dissipation
Grayscale ramp input
Grayscale ramp input
Standby Mode
65
33
1.8
0.95
50
95 mA
65 mA
10 mA
1.1 W
100 mW
AC TIMING CHARACTERISTICS
PLL Jitter (Note 5)
250 450 ps p-p
Sampling Phase Steps
5.6° per step
64
Sampling Phase Tempco
±1 ps/°C
Sampling Phase
Differential Nonlinearity
Degrees out-of-phase +360°www.DataSheet.co.kr
±3 °
HSYNC Frequency Range
10 150 kHz
fXTAL
tSETUP
Crystal Frequency Range
Data Valid Before Rising Edge of 20pF DATACLK load,
DATACLK
20pF DATA load
12 25 27 MHz
1.8 ns
tHOLD
Data Valid After Rising Edge of 20pF DATACLK load,
DATACLK
20pF DATA load
3.4
ns
NOTES:
3. Linearity tested at room temperature and established across commercial temperature range by correlation to characterization.
4. Supply current specified at max pixel rate (165MHz) with gray scale video applied.
5. Jitter tested at rated frequencies (110MHz, 150MHz and 165MHz) and at minimum frequency (10MHz).
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5 FN6760.0
September 12, 2008
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
ISL98003
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
0x04 Interrupt Status,
BITS
FUNCTION NAME
0 CH0 Sync Changed
Write a 1 to each bit to clear
it, 0xFF to clear all.
1 CH1 Sync Changed
2 N/A
3 N/A
4 Selected Input Channel
Disrupted
5 Selected Input Channel
Changed
0x05
Interrupt Mask Register,
(0xFF)
6 VSYNC INT
7 PADJ INT
0 CH0 Mask
1 CH1 Mask
2 N/A
3 N/A
www.DataSheet.co.kr
4 Input Disrupted Mask
5 Input Changed Mask
6 VSYNC INT Mask
7 PADJ INT Mask
DESCRIPTION
0: No change
1: CH0 activity or polarity changed
0: No change
1: CH1 activity or polarity changed
Ignore
Ignore
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
signal has changed (fast notification of a mode change).
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
period or pulse width has settled to a new value and can be
measured.
0: Default state
1: VSYNC occurred
0: Default state
1: Phase Adjustment function completed.
0: Generate interrupt if CH0 sync activity, polarity, period, or
pulse width changes.
1: Mask CH0 interrupt
0: Generate interrupt if CH1 sync activity, polarity, period, or
pulse width changes.
1: Mask CH1 interrupt
Set to 1
Set to 1
0: Generate interrupt if selected Input Channel’s sync inputs
are disrupted.
1: Mask Input Channel interrupt
0: Generate interrupt after selected Input Channel period or
pulse width settles to new value.
1: Mask Input Channel interrupt
0: Generate interrupt every VSYNC
1: Mask VSYNC Interrupt
0: Generate interrupt upon phase adjustment block request
completion.
1: Mask Phase adjustment interrupt
11
FN6760.0
September 12, 2008
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL98003.PDF ] | |
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