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PDF HD6437034B Data sheet ( Hoja de datos )
| Número de pieza | HD6437034B | |
| Descripción | (HD6417032 - HD6417034B) RISC ENGINE | |
| Fabricantes | Renesas | |
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REJ09B0272-0700
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7032, SH7034
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family/SH7030 Series
SH7032
www.DataSheet.co.kr
SH7034
SH7034B
HD6417032
HD6477034
HD6437034
HD6417034
HD6437034B
HD6417034B
Rev. 7.00
Revision Date: Jan 31, 2006
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
Organization of This Manual
Table 1 describes how this manual is organized. Figure 1 shows the relationships between the
sections within this manual.
Table 1
Category
Overview
CPU
Operating
Modes
Internal
Modules
Clock
Buses
Timers
Manual Organization
Section Title
1. Overview
2. CPU
Abbrevi-
ation
—
CPU
3. Operating Modes —
Contents
Features, internal block diagram, pin
layout, pin functions
Register configuration, data structure.
instruction features, instruction types,
instruction lists
MCU mode, PROM mode
4. Exception
Handling
—
Resets, address errors, interrupts, trap
instructions, illegal instructions
5. Interrupt
Controller
INTC
NMI interrupts, user break interrupts, IRQ
interrupts, on-chip module interrupts
6. User Break
Controller
UBC
Break address and break bus cycle
selection
7. Clock Pulse
Generator
CPG
Crystal pulse generator, duty correction
www.DataSheet.co.kr
circuit
8. Bus State
Controller
BSC
Division of memory space, DRAM
interface, refresh, wait state control, parity
control
9. Direct Memory
Access
Controller
DMAC
Auto request, external request, on-chip
peripheral module request, cycle steal
mode, burst mode
10. 16-Bit Integrated ITU
Timer Pulse Unit
Waveform output mode, input capture
function, counter clear function, buffer
operation, PWM mode, complementary
PWM mode, reset synchronized mode,
synchronized operation, phase counting
mode, compare match output mode
11. Programmable
Timing Pattern
Controller
TPC
Compare match output triggers, non-
overlap operation
12. Watchdog Timer WDT
Watchdog timer mode, interval timer mode
Rev. 7.00 Jan 31, 2006 page v of xxvi
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Item
Page
20.1.3 AC
Characteristics
486
(3) Bus Timing
Figure 20.9 Basic
Bus Cycle: Two-
State Access
Figure 20.12 (b) 490
DRAM Bus Cycle
(Short-Pitch, High-
Speed Page Mode:
Write)
Revision (See Manual for Details)
Note amended
Note 2. For tACC2, use tcyc × (n + 2) – 30 instead of tcyc × (n + 2) –
tAD (or tCSD1) – tRDS.
Figure amended
WRH, WRL,
WR (Write)
tWSD3
tWSD4
20.1.3 AC
Characteristics
502
(3) Bus Timing
Figure 20.22 Basic
Bus Cycle: Two-
State Access
Figure 20.25 (b) 506
DRAM Bus Cycle
(Short-Pitch, High-
Speed Page Mode:
Write)
AD15–AD0
DPH, DPL
(Write)
tWDD2
tWDH
tWPDD2
tWPDH
DPH, DPL
(Write)
Note amended
Note 2. For tACC2, use tcyc × (n + 2) – 44 instead of tcyc × (n + 2) –
t (or t ) – t .AD
CSD1
RDS
www.DataSheet.co.kr
Figure amended
WRH, WRL,
WR (Write)
tWSD3
tWSD4
AD15–AD0
DPH, DPL
(Write)
DPH, DPL
(Write)
tWDD2
tWDH
tWPDD2
tWPDH
Rev. 7.00 Jan 31, 2006 page xi of xxvi
Datasheet pdf - http://www.DataSheet4U.net/
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