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RTL8139C-LF の電気的特性と機能

RTL8139C-LFのメーカーはRealtek Microelectronicsです、この部品の機能は「3.3V Single-Chip Fast Ethernet Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 RTL8139C-LF
部品説明 3.3V Single-Chip Fast Ethernet Controller
メーカ Realtek Microelectronics
ロゴ Realtek Microelectronics ロゴ 




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RTL8139C-LF Datasheet, RTL8139C-LF PDF,ピン配置, 機能
RTL8139C
RTL8139C-LF
RTL8139CL
RTL8139CL-LF
3.3V SINGLE-CHIP FAST ETHERNET
CONTROLLER WITH POWER MANAGEMENT
www.DataSheet.co.kr
DATASHEET
Rev. 1.6
29 December 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
Datasheet pdf - http://www.DataSheet4U.net/

1 Page





RTL8139C-LF pdf, ピン配列
RTL8139C(L)
Datasheet
Table of Contents
1. General Description .............................................................................................................................................................1
2. Features.................................................................................................................................................................................2
3. Block Diagram ......................................................................................................................................................................3
4. Pin Assignments....................................................................................................................................................................4
4.1. Package and Version Identification................................................................................................................................4
5. Pin Descriptions....................................................................................................................................................................5
5.1. Power Management/Isolation Interface..........................................................................................................................5
5.2. PCI Interface ..................................................................................................................................................................5
5.3. FLASH/EEPROM Interface...........................................................................................................................................7
5.4. Power Pins......................................................................................................................................................................8
5.5. LED Interface.................................................................................................................................................................8
5.6. Attachment Unit Interface ..............................................................................................................................................8
5.7. Test and Other Pins ........................................................................................................................................................8
6. Register Descriptions ...........................................................................................................................................................9
6.1. Receive Status Register in Rx Packet Header ..............................................................................................................11
6.2. Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) .................................................................................12
6.3. ERSR: Early Rx Status Register (Offset 0036h, R) .....................................................................................................13
6.4. Command Register (Offset 0037h, R/W).....................................................................................................................13
6.5. Interrupt Mask Register (Offset 003Ch-003Dh, R/W).................................................................................................14
6.6. Interrupt Status Register (Offset 003Eh-003Fh, R/W).................................................................................................14
6.7. Transmit Configuration Register (Offset 0040h-0043h, R/W) ....................................................................................15
6.8. Receive Configuration Register (Offset 0044h-0047h, R/W)......................................................................................16
6.9. 9346CR: 93C46 (93C56) Command Register (Offset 0050h, R/W)............................................................................19
6.10. CONFIG 0: Configuration Register 0 (Offset 0051h, R/W) ....................................................................................19
6.11. CONFIG 1: Configuration Register 1 (Offset 0052h, R/W) ....................................................................................20
6.12. Media Status Register (Offset 0058h, R/W).............................................................................................................21
6.13. CONFIG 3: Configuration Register3 (Offset 0059h, R/W) .....................................................................................21
6.14. CONFIG 4: Configuration Register4 (Offset 005Ah, R/W)www.DataSheet.co.kr ....................................................................................23
6.15. Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) .............................................................................24
6.16. PCI Revision ID (Offset 005Eh, R)..........................................................................................................................24
6.17. Transmit Status of All Descriptors (TSAD) Register (Offset 0060h-0061h, R/W) .................................................24
6.18. Basic Mode Control Register (Offset 0062h-0063h, R/W)......................................................................................25
6.19. Basic Mode Status Register (Offset 0064h-0065h, R) .............................................................................................25
6.20. Auto-Negotiation Advertisement Register (Offset 0066h-0067h, R/W)..................................................................26
6.21. Auto-Negotiation Link Partner Ability Register (Offset 0068h-0069h, R)..............................................................27
6.22. Auto-Negotiation Expansion Register (Offset 006Ah-006Bh, R)............................................................................27
6.23. Disconnect Counter (Offset 006Ch-006Dh, R) ........................................................................................................27
6.24. False Carrier Sense Counter (Offset 006Eh-006Fh, R)............................................................................................28
6.25. NWay Test Register (Offset 0070h-0071h, R/W)....................................................................................................28
6.26. RX_ER Counter (Offset 0072h-0073h, R)...............................................................................................................28
6.27. CS Configuration Register (Offset 0074h-0075h, R/W)..........................................................................................28
6.28. Flash Memory Read/Write Register (Offset 00D4h-00D7h, R/W)..........................................................................29
6.29. Config5: Configuration Register 5 (Offset 00D8h, R/W) ........................................................................................29
6.30. Function Event Register (Offset 00F0h-00F3h, R/W) .............................................................................................30
6.31. Function Event Mask Register (Offset 00F4h-00F7h, R/W) ...................................................................................31
6.32. Function Present State Register (Offset 00F8h-00FBh, R) ......................................................................................31
6.33. Function Force Event Register (Offset 00FCh-00FFh, W) ......................................................................................32
7. EEPROM Contents (93C46 or 93C56).............................................................................................................................33
7.1. Summary of EEPROM Registers .................................................................................................................................35
7.2. Summary of EEPROM Power Management Registers ................................................................................................35
8. PCI Configuration Space Registers ..................................................................................................................................36
8.1. PCI Configuration Space Table....................................................................................................................................36
3.3V Single-Chip Fast Ethernet Controller w/Power Management
iii
Track ID: JATR-1076-21 Rev. 1.6
Datasheet pdf - http://www.DataSheet4U.net/


3Pages


RTL8139C-LF 電子部品, 半導体
2. Features
RTL8139C(L)
Datasheet
z 128 pin QFP/LQFP
z Integrated Fast Ethernet MAC, Physical chip, and
transceiver in one chip
z 10 Mb/s and 100 Mb/s operation
z Supports 10 Mb/s and 100 Mb/s N-way
Auto-negotiation operation
z PCI local bus single-chip Fast Ethernet controller
— Compliant to PCI Revision 2.2
— Supports PCI clock 16.75MHz-40MHz
— Supports PCI target fast back-to-back transaction
— Provides PCI bus master data transfers and PCI memory
space or I/O space mapped data transfers of
RTL8139C(L)'s operational registers
— Supports PCI VPD (Vital Product Data)
— Supports ACPI, PCI power management
z Supports CardBus. The CIS can be stored in 93C56 or
expansion ROM
z Supports up to 128K bytes Boot ROM interface for both
EPROM and Flash memory
z Supports 25MHz crystal or 25MHz OSC as the internal
clock source. The frequency deviation of either crystal or
OSC must be within 50 PPM.
z Compliant to PC99 standard
z Supports Wake-On-LAN function and remote wake-up
(Magic Packet*, LinkChg and Microsoft® wake-up
frame)
z Supports 4 Wake-On-LAN (WOL) signals (active high,
active low, positive pulse, and negative pulse)
z Supports auxiliary power-on internal reset, to be ready
for remote wake-up when main power still remains off
z Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space.
z Includes a programmable, PCI burst size and early
Tx/Rx threshold.
z Supports a 32-bit general-purpose timer with the
external PCI clock as clock source, to generate
timer-interrupt
z Contains two large (2Kbyte) independent receive and
transmit FIFO’s
z Advanced power saving mode when LAN function or
wakeup function is not used
z Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource configuration,
ID parameter, and VPD data. The 93C56 can also be
used to store the CIS data structure for CardBus
application.
z Supports LED pins for various network activity
indications
z Supports digital and analog loopback capability on both
ports
z Half/Full duplex capabilitywww.DataSheet.co.kr
z Supports Full Duplex Flow Control (IEEE 802.3x)
z 3.3V power supply with 5V tolerant I/Os.
* Third-party brands and names are the property of their
respective owners.
Note: The model number of the QFP package is RTL8139C. The LQFP package model number is RTL8139CL.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
2
Track ID: JATR-1076-21 Rev. 1.6
Datasheet pdf - http://www.DataSheet4U.net/

6 Page



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部品番号部品説明メーカ
RTL8139C-LF

3.3V Single-Chip Fast Ethernet Controller

Realtek Microelectronics
Realtek Microelectronics


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