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PDF NAU8401 Data sheet ( Hoja de datos )
| Número de pieza | NAU8401 | |
| Descripción | 24-bit Stereo Audio DAC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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NAU8401
Description
24-bit Stereo Audio DAC with Speaker Driver
emPowerAudio™
The NAU8401 is a low power, high quality audio output system for portable applications. In addition to
precision 24-bit stereo DACs, this device integrates a broad range of additional functions to simplify
implementation of complete audio systems. The NAU8401 includes drivers for speaker, headphone, and stereo
line outputs, and integrates mixing of the DAC outputs with analog input signals.
Advanced on-chip digital signal processing includes a 5-band equalizer, a 3-D audio enhancer, and a digital
limiter/dynamic range compressor function for the playback path. The digital interface can operate as either a
master or a slave. Additionally, an internal fractional-N PLL is available to generate accurate audio sample rate
clocks for the DAC derived from any available system clock from 8MHz through 33MHz.
The NAU8401 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate as low
as 1.7V to reduce power. The loudspeaker BTL output pair and two auxiliary line outputs can use a 5V supply to
increase output power capability, enabling the NAU8401 to drive 1 Watt into an external speaker. Internal
control registers enable flexible power conserving modes, shutting down sub-sections of the chip under software
control.
The NAU8401 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is
available upon request.
Key Features
DAC: 94dB SNR and -84dB THD (“A” weighted)
Integrated BTL speaker driver: 1W into 8Ω
Integrated head-phone driver: 40mW into 16Ω
Integrated line inputs and line outputs
On-chip high resolution fractional-N PLL
Integrated DSP with specific functions:
5-band equalizer
3-D audio enhancement
Automatic level control
Audio level limiter/dynamic range compressor
Standard audio interfaces: PCM and I2S
Serial control interfaces with read/write capability
Supports audio sample rates from 8kHz to 48kHz
Applications
Personal Navigation Devices
Personal Media Players
Personal Navigation Devices
Portable Game Players
Portable TVs
Datasheet Rev 2.5
Page 1 of 69
March, 2014
1 page  
NAU8401
Table of Contents
1 GENERAL DESCRIPTION .............................................................................................................................10
2 POWER SUPPLY.............................................................................................................................................12
3 INPUT PATH DETAILED DESCRIPTION....................................................................................................13
3.1 Analog Input Impedance and Variable Gain Stage Topology .....................................................................13
3.2 Programmable Reference Voltage Controls ...............................................................................................14
4 DAC DIGITAL BLOCK ..................................................................................................................................15
4.1 DAC Soft Mute ...........................................................................................................................................15
4.2 DAC AutoMute ...........................................................................................................................................15
4.3 DAC Sampling / Oversampling Rate, Polarity Control, Digital Passthrough ...............................................15
4.4 DAC Digital Volume Control and Update Bit Functionality .........................................................................16
4.5 DAC Automatic Output Peak Limiter / Volume Boost .................................................................................16
4.6 5-Band Equalizer........................................................................................................................................17
4.7 3D Stereo Enhancement ............................................................................................................................18
4.8 DAC Output A-law and µ-law Expansion...................................................................................................19
4.9 8-bit Word Length.......................................................................................................................................19
5 ANALOG OUTPUTS.......................................................................................................................................20
5.1 Main Mixers (LMAIN MIX and RMAIN MIX)................................................................................................20
5.2 Auxiliary Mixers (AUX1 MIXER and AUX2 MIXER)....................................................................................21
5.3 Right Speaker Submixer ............................................................................................................................21
5.4 Headphone Outputs (LHP and RHP) .........................................................................................................22
5.5 Speaker Outputs ........................................................................................................................................23
5.6 Auxiliary Outputs ........................................................................................................................................24
6 MISCELLANEOUS FUNCTIONS ..................................................................................................................24
6.1 Slow Timer Clock .......................................................................................................................................24
6.2 General Purpose Inputs and Outputs (GPIO1, GPIO2, GPIO3) and Jack Detection..................................25
6.3 Automated Features Linked to Jack Detection ...........................................................................................25
7 CLOCK SELECTION AND GENERATION ..................................................................................................26
7.1 Phase Locked Loop (PLL) General Description .........................................................................................27
7.2 CSB/GPIO1 as PLL output .........................................................................................................................28
8 CONTROL INTERFACES...............................................................................................................................29
8.1 Software Reset...........................................................................................................................................29
8.2 Selection of Control Mode ..........................................................................................................................29
8.3 2-Wire-Serial Control Mode (I2C Style Interface)........................................................................................29
8.4 2-Wire Protocol Convention........................................................................................................................30
8.5 2-Wire Write Operation...............................................................................................................................31
8.6 2-Wire Read Operation ..............................................................................................................................32
8.7 SPI Control Interface Modes ......................................................................................................................33
8.8 SPI 3-Wire Write Operation ........................................................................................................................33
8.9 SPI 4-Wire 24-bit Write and 32-bit Read Operation...................................................................................33
8.10 SPI 4-Wire Write Operation ......................................................................................................................34
8.11 SPI 4-Wire Read Operation........................................................................................................................35
9 DIGITAL AUDIO INTERFACES ...................................................................................................................36
9.1 Right-Justified Audio Data ..........................................................................................................................36
9.2 Left-Justified Audio Data ............................................................................................................................37
9.3 I2S Audio Data............................................................................................................................................37
9.4 PCM A Audio Data .....................................................................................................................................38
Datasheet Rev 2.5
Page 5 of 69
March, 2014
5 Page 
NAU8401
1.1.3 DAC and Digital Signal Processing
Each left and right channel has an independent high quality DAC associated with it. These are high performance,
24-bit delta-sigma converters that are suitable for a very wide range of applications.
The DAC functions are each individually supported by powerful analog mixing and routing. The DAC blocks
are also supported by advanced digital signal processing subsystems that enable a very wide range of
programmable signal conditioning and signal optimizing functions. All digital processing is with 24-bit
precision, as to minimize processing artifacts and maximize the audio dynamic range supported by the
NAU8401.
The DACs are supported by a programmable limiter/DRC (Dynamic Range Compressor). This is useful to
optimize the output level for various applications and for use with small loudspeakers. This is an optional
feature that may be programmed to limit the maximum output level and/or boost an output level that is too small.
Digital signal processing is also provided for a 3D Audio Enhancement function, and for a 5-Band Equalizer.
These features are optional, and are programmable over wide ranges. This pair of digital processing features
may be applied jointly to the DAC audio path, or be jointly disabled from the DAC audio path.
1.1.4 Programmable Voltage Reference
The filtered Vref pin is buffered and scaled to create a low-noise programmable DC output voltage. This output
may be used for a wide range of purposes, such as providing a DC bias for other amplifiers and components in
the system.
1.1.5 Digital Interfaces
Command and control of the device is accomplished using a 2-wire/3-wire/4-wire serial control interface. This
is a simple, but highly flexible interface that is compatible with many commonly used command and control
serial data protocols and host drivers.
Digital audio input/output data streams are transferred to and from the device separately from command and
control. The digital audio data interface supports either I2S or PCM audio data protocols, and is compatible with
commonly used industry standard devices that follow either of these two serial data formats.
1.1.6 Clock Requirements
The clocking signals required for the audio signal processing, audio data I/O, and control logic may be provided
externally, or by optional operation of a built-in PLL (Phase Locked Loop). An external master clock (MCLK)
signal must be active for analog audio logic paths to align with control register updates, and is required as the
reference clock input for the PLL, if the PLL is used.
The PLL is provided as a low cost, zero external component count optional method to generate required clocks
in almost any system. The PLL is a fractional-N divider type design, which enables generating accurate desired
audio sample rates derived from a very wide range of commonly available system clocks.
The frequency of the system clock provided as the PLL reference frequency may be any stable frequency in the
range between 8MHz and 33MHz. Because the fractional-N multiplication factor is a very high precision 24-bit
value, any desired sample rate supported by the NAU8401 can be generated with very high accuracy, typically
limited by the accuracy of the external reference frequency. Reference clocks and sample rates outside of these
ranges are also possible, but may involve performance tradeoffs and increased design verification.
Datasheet Rev 2.5
Page 11 of 69
March, 2014
11 Page | ||
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