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PDF IR22141SSPBF Data sheet ( Hoja de datos )
| Número de pieza | IR22141SSPBF | |
| Descripción | HALF-BRIDGE GATE DRIVER IC | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Data Sheet No. PD60349 revL
IR21141SSPbF/IR22141SSPbF
HALF-BRIDGE GATE DRIVER IC
Features
• Floating channel up to 600 V or 1200 V
• Soft over-current shutdown
• Synchronization signal to synchronize shutdown with the other phases
• Integrated desaturation detection circuit
• Two stage turn on output for di/dt control
• Separate pull-up/pull-down output drive pins
• Matched delay outputs
• Undervoltage lockout with hysteresis band
• Lead free
Description
The IR21141/IR22141 gate driver family is suited to drive a single half bridge
in power switching applications. These drivers provide high gate driving
capability (2 A source, 3 A sink) and require low quiescent current, which
allows the use of bootstrap power supply techniques in medium power
systems. These drivers feature full short circuit protection by means of power
transistor desaturation detection and manage all half-bridge faults by
smoothly turning off the desaturated transistor through the dedicated soft
shutdown pin, therefore preventing over-voltages and reducing
electromagnetic emissions. In multi-phase systems, the IR21141/IR22141
drivers communicate using a dedicated local network (SY_FLT and
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FAULT/SD signals) to properly manage phase-to-phase short circuits. The
system controller may force shutdown or read device fault state through the
3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity
from DC-bus noise, the control and power ground use dedicated pins
enabling low-side emitter current sensing as well. Undervoltage conditions in
floating and low voltage circuits are managed independently.
Product Summary
VOFFSET
IO+/- (min)
VOUT
Deadtime matching (max)
Deadtime (typ)
Desat blanking time (typ)
DSH, DSL input voltage
threshold (typ)
Soft shutdown time (typ)
600 V or
1200 V max.
1.0 A / 1.5 A
10.4 V – 20 V
75 ns
330 ns
3 µs
8.0 V
9.25 µs
Package
24-Lead SSOP
Typical connection
www.irf.com
14-Aug-09
1
© 2009 International Rectifier
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
IR21141/IR22141SSPbF
AC Electrical Characteristics
VCC = VBS = 15 V, VS = VSS and TA = 25 °C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units
Test Conditions
ton
toff
tr
tf
ton1
tDESAT1
Turn on propagation delay
Turn off propagation delay
Turn on rise time (CLOAD=1 nF)
Turn off fall time (CLOAD=1 nF)
Turn on first stage duration time
220 440 660
220 440 660
— 24 —
—7—
120 200 280
DSH to HO soft shutdown propagation delay at HO
turn on
2000
3300
4600
VIN = 0 & 1, VS = 0 V to 600 V
or 1200 V,
HOP shorted to HON, LOP
shorted to LON, Fig. 7
Fig. 8
VHIN= 1 V
tDESAT2
DSH to HO soft shutdown propagation delay after
blanking
1050
—
—
VDESAT = 15 V, Fig. 10
tDESAT3
DSL to LO soft shutdown propagation delay at LO
turn on
2000
3300
4600
VLIN = 1 V
tDESAT4
tDS
tSS
tSY_FLT,
DESAT1
tSY_FLT,
DESAT2
tSY_FLT,
DESAT3
tSY_FLT,
DESAT4
tBL
DSL to LO soft shutdown propagation delay after
blanking
Soft shutdown minimum pulse width of desat
Soft shutdown duration period
DSH to SY_FLT propagation delay at HO turn on
1050 — —
1000 — —
5700 9250 13500
— 3600 —
ns
VDESAT = 15 V, Fig. 10
Fig. 9
VDS=15 V, Fig. 9
VHIN = 1 V
DSH to SY_FLT propagation delay after blanking 1300 — —
VDS = 15 V, Fig. 10
DSL to SY_FLT propagation delay at LO turn on
—
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3050
—
DSL to SY_FLT propagation delay after blanking 1050 — —
DS blanking time at turn on
— 3000 —
VLIN = 1 V
VDESAT=15 V, Fig. 10
VHIN = VLIN = 1 V, VDESAT=15 V,
Fig. 10
Deadtime/Delay Matching Characteristics
DT Deadtime
— 330 —
Fig. 11
MDT
Deadtime matching, MDT=DTH-DTL
— — 75
External DT = 0 s, Fig. 11
PDM
Propagation delay matching,
Max (ton, toff) – Min (ton, toff)
— — 75
External DT > 500 ns, Fig. 7
www.irf.com
© 2009 International Rectifier
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
IR21141/IR22141SSPbF
HO/LO Status
0
1
SSD
LO/HO
LOn-1/HOn-1
HOP/LOP HON/LON
SSDH/SSDL
HiZ 0
HiZ
1 HiZ
HiZ
HiZ HiZ
0
Output follows inputs (in=1->out=1, in=0->out=0)
Output keeps previous status
Logic Table: Output Drivers Status Description
INPUTS
Operation Hin Lin FLT_CLR
Shutdown
Fault Clear
Fault Cleared
Normal
Operation
Anti Shoot
Through
Soft
Shutdown
(entering)
Soft
Shutdown
(finishing)
Freeze
Undervoltage
X
HIN
HIN
1
0
0
1
1
0
X
X
X
X
X
X
LIN
LIN
0
1
0
1
0
1
X
X
X
LIN
X
X
1
0
0
0
0
0
0
0
0
X
X
X
INPUT/OUTPUT
______
SY_FLT
SSD: desat (out)
HOLD: freezing
(in)
X
X†
X
1
1
_________
FAULT/SD
SD: shutdown (in)
FAULT: diagnostic
(out)
0 (SD)
(FAULT)
1 ††
1
1
11
1
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(SSD)
(SSD)
(SSD)
1
1
1
(FAULT)
(SSD)
(FAULT)
0 (HOLD)
1
1
1
1
0 (FAULT)
Undervoltage
Yes: V< UV
threshold
No : V> UV
threshold
X: don’t care
VCC
VBS
XX
No No
No No
No No
No No
No No
No No
No No
No No
No No
No No
No No
No Yes
Yes X
OUTPUTS
HO LO
0
HO
HO
1
0
0
0
SSD
0
0
0
HOn-1
0
0
0
LO
LO
0
1
0
0
0
SSD
0
0
LOn-1
LO
0
† SY_FLT automatically resets after the SSD event is over, without requiring FLT_CLR to be asserted. To
avoid FLT_CLR conflicting with the SSD sequence of operations, in the event of a SSD during normal
operation it is recommended not to apply FLT_CLR while SY_FLT is active. At power supply start-up
instead, it is recommended to keep FLT_CLR active to prevent spurious diagnostic signals being
generated, as described in section 1.1 Start-Up Sequence and in section 1.4.5 Fault Management at
Start-up.
†† Holding FLT_CLR high all time will not allow the gate driver to latch the FAULT status and migth
compromise power system protection.
www.irf.com
11
© 2009 International Rectifier
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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