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ISLA212P50 の電気的特性と機能

ISLA212P50のメーカーはIntersilです、この部品の機能は「500MSPS ADC」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISLA212P50
部品説明 500MSPS ADC
メーカ Intersil
ロゴ Intersil ロゴ 




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ISLA212P50 Datasheet, ISLA212P50 PDF,ピン配置, 機能
www.DataSheet.co.kr
12-Bit, 500MSPS ADC
ISLA212P50
The ISLA212P50 is a 12-bit, 500MSPS analog-to-digital converter
designed with Intersil’s proprietary FemtoCharge™ technology on
a standard CMOS process. The ISLA212P50 is part of a
pin-compatible portfolio of 12 to 16-bit A/Ds with maximum
sample rates ranging from 130MSPS to 500MSPS.
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single 500MHz
conversion clock is presented to the converter, and all interleave
clocking is managed internally. The proprietary Intersil Interleave
Engine (I2E) performs automatic correction of offset, gain, and
sample time mismatches between the unit ADCs to optimize
performance.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue offline and
continuous calibration commands as well as configure many
dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA212P50 is available in a 72 Ld QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
• SNR @ 500MSPS
= 70.3dBFS fIN = 30MHz
= 68.7dBFS fIN = 363MHz
• SFDR @ 500MSPS
= 84dBc fIN = 30MHz
= 76dBc fIN = 363MHz
• Total Power Consumption = 823mW @ 500MSPS
Features
• Automatic Fine Interleave Correction Calibration
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKP
CLKN
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
VINP
VINN
VCM
SHA
SHA
12-BIT
250 MSPS
ADC
VREF
Gain, Offset
and Skew
Adjustments
I2E
DIGITAL
ERROR
CORRECTION
D[11:0]P
D[11:0]N
ORP
ORN
12-BIT
250 MSPS
ADC
VREF
+
SPI
CONTROL
Pin-Compatible Family
MODEL
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
May 25, 2011
FN7843.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/

1 Page





ISLA212P50 pdf, ピン配列
www.DataSheet.co.kr
ISLA212P50
Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)
PIN NUMBER
10, 11
15
16
18
22, 23
24, 25
28, 29
30, 31
33, 34
35, 36
37, 38
39, 40
41, 42
43, 44
46
47, 48
49, 50
51, 52
53, 54
55, 56
63, 64
66
67
68
69
Exposed Paddle
LVDS PIN NAME
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D11N, D11P
D10N, D10P
D9N, D9P
D8N, D8P
D7N, D7P
D6N, D6P
D5N, D5P
D4N, D4P
RLVDS
CLKOUTN, CLKOUTP
D3N, D3P
D2N, D2P
D1N, D1P
D0N, D0P
ORN, ORP
SDO
CSB
SCLK
SDIO
AVSS
LVDS PIN FUNCTION
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bit 11 (MSB) Output Complement, True
LVDS Bit 10 Output Complement, True
LVDS Bit 9 Output Complement, True
LVDS Bit 8 Output Complement, True
LVDS Bit 7 Output Complement, True
LVDS Bit 6 Output Complement, True
LVDS Bit 5 Output Complement, True
LVDS Bit 4 Output Complement, True
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
LVDS Clock Output Complement, True
LVDS Bit 3 Output Complement, True
LVDS Bit 2 Output Complement, True
LVDS Bit 1 Output Complement, True
LVDS Bit 0 (LSB) Output Complement, True
LVDS Over Range Complement, True
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
3 FN7843.1
May 25, 2011
Datasheet pdf - http://www.DataSheet4U.net/


3Pages


ISLA212P50 電子部品, 半導体
www.DataSheet.co.kr
ISLA212P50
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA212P50IRZ
ISLA212P50 IRZ
-40 to +85
72 Ld QFN
L72.10x10E
ISLA214P50IR72EV1Z
14-bit 500MSPS ADC Evaluation Board (This 14-bit ADC evaluation board can be configured for 12-bit testing.)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate--e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA212P50. For more information on MSL please see Tech Brief TB363.
6 FN7843.1
May 25, 2011
Datasheet pdf - http://www.DataSheet4U.net/

6 Page



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部品番号部品説明メーカ
ISLA212P50

500MSPS ADC

Intersil
Intersil


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