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ISL78228 の電気的特性と機能

ISL78228のメーカーはIntersil Corporationです、この部品の機能は「Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL78228
部品説明 Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL78228 Datasheet, ISL78228 PDF,ピン配置, 機能
DATASHEET
Dual 800mA Low Quiescent Current 2.25MHz High
Efficiency Synchronous Buck Regulator
ISL78228
The ISL78228 is a high efficiency, dual synchronous step-down
DC/DC regulator that can deliver up to 800mA continuous
output current per channel. The supply voltage range of 2.75V
to 5.5V allows for the use of a 3.3V or 5V input. The current
mode control architecture enables very low duty cycle
operation at high frequency with fast transient response and
excellent loop stability. The ISL78228 operates above the AM
radio band as well as the 2.25MHz switching frequency,
allowing for the use of small, low cost inductors and
capacitors. Each channel is optimized for generating an output
voltage as low as 0.6V.
The ISL78228 has a user configurable mode of
operation-forced PWM mode and PFM mode. The forced PWM
mode operation reduces noise and RF interference while the
PFM mode operation provides high efficiency by reducing
switching losses at light loads. In PFM mode of operation, both
channels draw a total quiescent current of only 30µA, hence
enabling high light-load efficiency in order to maximize battery
life.
The ISL78228 offers a 1ms power-good (PG) to monitor both
outputs at power-up. When shut down, ISL78228 discharges
the output capacitor. Other features include internal digital
soft-start, enable for power sequence, overcurrent protection,
and thermal shutdown. The ISL78228 is offered in a
3mmx3mm 10 Ld DFN package with 1mm maximum height.
The complete converter occupies less than 1.8cm2 area.
The ISL78228 is AEC-Q100 qualified and is rated for the
automotive temperature range (-40°C to +105°C).
Features
• Internal current mode compensation
• 100% maximum duty cycle for lowest dropout
• Selectable forced PWM mode and PFM mode
• External synchronization up to 4MHz
• Start-up with prebiased output
• Soft-stop output discharge during disable
• Internal digital soft-start - 2ms
• Power-good (PG) output with 1ms delay
• AEC-Q100 qualified
• Pb-free (RoHS compliant)
Applications
• DC/DC POL modules
• µC/µP, FPGA and DSP power
• Rear camera systems
• Navigation systems
• Infotainment systems
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
ISL78228
IOUT CH1
(A)
0.8
IOUT CH2
(A)
0.8
ADJ or FIXED
VOUT
PACKAGE
ADJ 10 Ld 3x3 DFN
ISL78322
2.0
1.7
ADJ 12 Ld 4x3 DFN
100
90
80 2.5VOUT-PFM
70 1.8VOUT-PFM
2.5VOUT-PWM
60
50
40
0.0
1.8VOUT- PWM
VIN = 5V
0.1 0.2
0.3 0.4 0.5
OUTPUT LOAD (A)
0.6
FIGURE 1. EFFICIENCY CHARACTERISTICS CURVE
0.7
0.8
February 26, 2016
FN7849.4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL78228 pdf, ピン配列
Pin Configuration
ISL78228
ISL78228
(10 LD 3x3 DFN)
TOP VIEW
FB1 1
EN1 2
VIN 3
LX1 4
NC 5
PAD
10 FB2
9 EN2
8 PG
7 LX2
6 SYNC
Pin Descriptions
PIN#
1
2
3
4
5
6
7
8
9
10
-
PIN NAME
FB1
EN1
VIN
LX1
NC
SYNC
LX2
PG
EN2
FB2
PAD
DESCRIPTION
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any
voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1
regulator output voltage.
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge output
capacitor when driven to low. Do not leave this pin floating.
Input supply voltage. Connect 10µF ceramic capacitor to power ground.
Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.
Recommended to connect this pin to the exposed pad.
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode.
Connect to an external function generator for synchronization and negative edge trigger. Do not leave this pin floating.
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the VOUT1 and VOUT2 voltages.
There is an internal 1MΩ pull-up resistor.
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shut down the VOUT2 and discharge output
capacitor when driven to low. Do not leave this pin floating.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any
voltage between the power-rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage.
The exposed pad must be connected to PGND for proper electrical performance. Add as many vias as possible for optimal thermal
performance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL78228ARZ
8228
-40 to +105
10 Ld 3x3 DFN
L10.3x3C
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78228. For more information on MSL please see techbrief TB363.
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February 26, 2016


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ISL78228 電子部品, 半導体
ISL78228
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to
5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA.
100 100
90 90
80
2.5VOUT
70
1.2VOUT
60
50
1.5VOUT
1.8VOUT
80
2.5VOUT
70
1.2VOUT
60
50
1.8VOUT
1.5VOUT
40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD 2.25MHz 3.3VIN PWM
0.8
400.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD 2.25MHz 3.3VIN PFM
0.8
100
90
80
2.5VOUT
70
3.3VOUT
1.5VOUT
60
1.2VOUT
1.8VOUT
50
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD 2.25MHz 5VIN PWM
0.8
100
90
80
70
1.5VOUT
60
1.2VOUT
1.8VOUT
50
3.3VOUT
2.5VOUT
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD 2.25MHz 5VIN PFM
0.8
0.30
0.25
0.20
3.3VIN - PWM
5VIN - PWM
0.15
0.10
5VIN - PFM
0.05
3.3VIN - PFM
0.00
0.0
0.1 0.2 0.3 0.4 0.5 0.6
OUTPUT LOAD (A)
0.7 0.8
FIGURE 7. POWER DISSIPATION vs LOAD 2.25MHz, 1.8VOUT PWM
1.23
1.22
5VIN PFM
1.21
5VIN PWM
1.20
1.19
1.18
3.3V VIN PWM
3.3V VIN PFM
1.17
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
OUTPUT LOAD (A)
FIGURE 8. VOUT REGULATION vs LOAD 2.25MHz, 1.2VOUT PFM
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