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PDF K4B2G1646C Data sheet ( Hoja de datos )
| Número de pieza | K4B2G1646C | |
| Descripción | 2Gb C-die DDR3 SDRAM | |
| Fabricantes | Samsung semiconductor | |
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1. K4B2G1646C datasheet  Hay una vista previa y un enlace de descarga de K4B2G1646C (archivo pdf) en la parte inferior de esta página. Total 64 Páginas | ||
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Rev. 1.11, Nov. 2010
K4B2G1646C
2Gb C-die DDR3 SDRAM Only x16
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
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K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
1. Ordering Information
[ Table 1 ] Samsung 2Gb DDR3 C-die ordering information table
Organization DDR3-1066(7-7-7)
DDR3-1333(9-9-9)5 DDR3-1600(11-11-11)4 DDR3-1866(13-13-13)3 DDR3-2133(14-14-14)2 Package
128Mx16 K4B2G1646C-HCF8 K4B2G1646C-HCH9 K4B2G1646C-HCK0 K4B2G1646C-HCMA
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward Compatible to DDR3-1866(13-13-13), DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
3. Backward Compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
4. Backward Compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
5. Backward Compatible to DDR3-1066(7-7-7)
K4B2G1646C-HCNB
96 FBGA
2. Key Features
[ Table 2 ] 2Gb DDR3 C-die Speed bins
Speed
DDR3-800
6-6-6
DDR3-1066
7-7-7
tCK(min)
2.5
1.875
CAS Latency
6
7
tRCD(min)
15
13.125
tRP(min)
15
13.125
tRAS(min)
37.5
37.5
tRC(min)
52.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
DDR3-1866
13-13-13
1.07
13
13.91
13.91
34
47.91
DDR3-2133
14-14-14
0.935
14
13.09
13.09
33
46.09
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
900MHz fCK for 1866Mb/sec/pin, 1000MHz fCK for 2133Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13,14
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600), 9(DDR3-1866) and
10(DDR3-2133)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 2Gb DDR3 SDRAM C-die is organized as a 16Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 2133Mb/sec/pin (DDR3-2133) for general applica-
tions.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 2Gb DDR3 C-die device is available in 96balls FBGA(x16).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
-5-
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K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address
Symbol
Parameter
DDR3-800/1066/1333/1600
Min.
Max.
DDR3-1866/2133
Min.
Max.
Unit NOTE
VIH.CA(DC100) DC input logic high
VREF + 100 VDD VREF + 100 VDD mV 1,5
VIL.CA(DC100) DC input logic low
VSS
VREF - 100
VSS
VREF - 100
mV 1,6
VIH.CA(AC175) AC input logic high
VREF + 175
Note 2
-
- mV 1,2,7
VIL.CA(AC175) AC input logic low
Note 2
VREF - 175
-
- mV 1,2,8
VIH.CA(AC150) AC input logic high
VREF+150
Note 2
-
- mV 1,2,7
VIL.CA(AC150) AC input logic low
Note 2
VREF-150
-
- mV 1,2,8
VIH.CA(AC135) AC input logic high
-
-
VREF + 135
Note 2
mV 1,2,7
VIL.CA(AC135) AC input logic low
-
-
Note 2
VREF - 135
mV 1,2,8
VIH.CA(AC125) AC input logic high
-
-
VREF+125
Note 2
mV 1,2,7
VIL.CA(AC125) AC input logic low
-
-
Note 2
VREF-125
mV 1,2,8
VREFCA(DC)
Reference Voltage for ADD,
CMD inputs
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V 3,4
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135) and VIH.CA(AC125); VIH.CA(AC175) value is used when VREF + 175mV is referenced
, VIH.CA(AC150) value is used when VREF + 150mV is referenced, VIH.CA(AC135) value is used when VREF + 135mV is referenced and VIH.CA(AC125) value is used when
VREF + 125mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when VREF - 175mV is refer-
enced, VIL.CA(AC150) value is used when VREF - 150mV is referenced, VIL.CA(AC135) value is used when VREF - 135mV is referenced and VIL.CA(AC125) value is used
when VREF - 125mV is referenced.
[ Table 8 ] Single-ended AC & DC input levels for DQ and DM
Symbol
Parameter
DDR3-800/1066
Min.
Max.
DDR3-1333/1600
Min.
Max.
DDR3-1866/2133
Min.
Max.
Unit NOTE
VIH.DQ(DC100) DC input logic high
VREF + 100
VDD
VREF + 100
VDD
VREF + 100
VDD
mV 1,5
VIL.DQ(DC100) DC input logic low
VSS VREF - 100 VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.DQ(AC175) AC input logic high
VREF + 175
NOTE 2
-
-
-
- mV 1,2,7
VIL.DQ(AC175) AC input logic low
NOTE 2
VREF - 175
-
-
-
- mV 1,2,8
VIH.DQ(AC150) AC input logic high
VREF + 150
NOTE 2
VREF + 150
NOTE 2
-
- mV 1,2,7
VIL.DQ(AC150) AC input logic low
NOTE 2
VREF - 150
NOTE 2
VREF - 150
-
- mV 1,2,8
VIH.DQ(AC135) AC input logic high
-
-
-
-
VREF + 135
NOTE 2
mV 1,2,7
VIL.DQ(AC135) AC input logic low
-
-
-
-
NOTE 2
VREF - 135 mV 1,2,8
VREFDQ(DC)
Reference Voltage for DQ,
DM inputs
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) and VIH.DQ(AC135) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced,
VIH.DQ(AC150) value is used when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when
VREF - 150mV is referenced.
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