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PDF IS64WV25616BLL Data sheet ( Hoja de datos )
| Número de pieza | IS64WV25616BLL | |
| Descripción | 256K X 16 High Speed Asynchronous CMOS Static Ram | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS61WV25616ALL/ALSwww.DataSheet.co.kr
IS61WV25616BLL/BLS
IS64WV25616BLL/BLS
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
JULY 2010
FEATURES
DESCRIPTION
HIGH SPEED: (IS61/64WV25616ALL/BLL)
• High-speed access time: 8, 10, 20 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
LOW POWER: (IS61/64WV25616ALS/BLS)
The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx
are high-speed, 4,194,304-bit static RAMs organized as
262,144 words by 16 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields high-performance and low power consumption de-
vices.
• High-speed access time: 25, 35, 45 ns
• Low Active Power: 35 mW (typical)
• Low Standby Power: 0.6 mW (typical)
CMOS standby
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• Single power supply
— VDD 1.65V to 2.2V (IS61WV25616Axx)
— VDD 2.4V to 3.6V (IS61/64WV25616Bxx)
• Fully static operation: no clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV25616Axx/Bxx and IS64WV25616Bxx are
packaged in the JEDEC standard 44-pin TSOP Type II and
48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE CONTROL
WE CIRCUIT
UB
LB
256K x 16
MEMORY ARRAY
COLUMN I/O
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
1
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
OutputLoad
Unit
(2.4V-3.6V)
0V to 3V
1V/ ns
1.5V
See Figures 1 and 2
Unit
(3.3V + 10%)
0V to 3V
1V/ ns
1.5V
See Figures 1 and 2
Unit
(1.65V-2.2V)
0V to 1.8V
1V/ ns
0.9V
See Figures 1 and 2
AC TEST LOADS
OUTPUT
ZO = 50Ω
50Ω
1.5V
30 pF
Including
jig and
scope
Figure 1.
3.3V
319 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
353 Ω
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
ADDRESS
DOUT
t RC
PREVIOUS DATA VALID
t OHA
t AA
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
ADDRESS
OE
CE
LB, UB
tLZCE
DOUT
tLZB
HIGH-Z
tRC
tAA tOHA
tDOE
tLZOE
tACE
tHZOE
tHZCE
tBA tRC
tHZB
DATA VALID
VDD
Supply
Current
tPU
50%
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
tPD
50%
ICC
ISB
UB_CEDR2.eps
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
11
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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| PDF Descargar | [ Datasheet IS64WV25616BLL.PDF ] | |
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