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RTL8201CL-LF の電気的特性と機能

RTL8201CL-LFのメーカーはRealtekです、この部品の機能は「SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 RTL8201CL-LF
部品説明 SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER
メーカ Realtek
ロゴ Realtek ロゴ 




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RTL8201CL-LF Datasheet, RTL8201CL-LF PDF,ピン配置, 機能
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RTL8201CL
RTL8201CL-LF
RTL8201CL-VD
RTL8201CL-VD-LF
SINGLE-CHIP/SINGLE-PORT
10/100M FAST ETHERNET PHYCEIVER
DATASHEET
Rev. 1.24
04 November 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw

1 Page





RTL8201CL-LF pdf, ピン配列
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REVISION HISTORY
Revision
1.0
1.1
Release Date
2003/06/09
2003/09/26
1.2 2004/01/20
1.21 2004/10/12
1.22 2005/04/11
1.23 2005/07/29
1.24 2005/11/04
RTL8201CL
Datasheet
Summary
First release.
Minor cosmetic changes.
Modify LED Pin behavior.
Add LED multi-mode definition (7.5 LED and PHY Address
Configuration, page 19).
Add Power dissipation info (Table 31).
Bit <0:8> default setting changed to 0 (Table 9).
Bit <0:13> default setting changed to 0 (Table 9).
Bit <5:7> default setting changed to 0 (Table 14).
Bit <17:5> default setting changed to 1 (Table 17).
Bit <25:0> default setting changed to 0 (Table 20).
Bit <25:1> default setting changed to 0 (Table 20).
Bit <25:11~7> default setting changed to 00001 (Table 20).
Package additions. See section 10, Ordering Information, page 33.
Correction to Table 18, Register 18 RX_ER Counter (REC), page 13.
Correction to Table 39, Transformer Characteristics, page 30.
Added lead (Pb)-free package identification information on page 3 and on
page 33.
Corrected error in 7.8.3 10Base-T TX/RX, page 21 (10Base-T Transmit
Function _ clock at 25MHz => clock at 2.5MHz).
Corrections to Table 32, Input Voltage: Vcc, page 23.
Vcc _ TTL Voh _ Minimum 0.9*Vcc => Minimum 0.65*Vcc
Vcc _ TTL Vol _ Maximum 0.1*Vcc => Maximum 0.3*Vcc
Vcc _ TTL Ioz _ Minimum -10uA => Minimum -110uA
Vcc _ Iin _ Minimum -1.0uA => Minimum -110uA
Vcc _ Iin _ Maximum 1.0uA => Maximum 100uA
Revised Table 1, page 4 (pins 2, 3, 4, 5, 6, and 25).
Corrected Table 17, page 12 (bits 17:6 and 17:5).
Corrected Table 18, page 13 (mode).
Revised Table 32, page 23 (IIN, IPL, IPH).
Revised Table 33, page 24 (t8).
Revised Table 34, page 25 (t6, t7, t9).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
iii
Track ID: JATR-1076-21 Rev. 1.24


3Pages


RTL8201CL-LF 電子部品, 半導体
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RTL8201CL
Datasheet
Table 23. UTP Mode and MII Interface ......................................................................................................16
Table 24. UTP Mode and SNI Interface......................................................................................................17
Table 25. Fiber Mode and MII Interface .....................................................................................................17
Table 26. Auto-Negotiation Mode Pin Settings ..........................................................................................18
Table 27. LED Definitions ..........................................................................................................................19
Table 28. Power Saving Mode Pin Settings ................................................................................................20
Table 29. Absolute Maximum Ratings........................................................................................................23
Table 30. Operating Conditions...................................................................................................................23
Table 31. Power Dissipation........................................................................................................................23
Table 32. Input Voltage: Vcc.......................................................................................................................23
Table 33. MII Transmission Cycle Timing .................................................................................................24
Table 34. MII Reception Cycle Timing.......................................................................................................25
Table 35. SNI Transmission Cycle Timing .................................................................................................27
Table 36. SNI Reception Cycle Timing ......................................................................................................28
Table 37. MDC/MDIO Timing....................................................................................................................29
Table 38. Crystal Characteristics.................................................................................................................30
Table 39. Transformer Characteristics ........................................................................................................30
Table 40. Ordering Information...................................................................................................................33
List of Figures
Figure 1. Block Diagram .............................................................................................................................2
Figure 2. Pin Assignments...........................................................................................................................3
Figure 3. Read Cycle .................................................................................................................................15
Figure 4. Write Cycle ................................................................................................................................15
Figure 5. LED and PHY Address Configuration.......................................................................................19
Figure 6. MII Transmission Cycle Timing-1.............................................................................................24
Figure 7. MII Transmission Cycle Timing-2.............................................................................................25
Figure 8. MII Reception Cycle Timing-1 ..................................................................................................26
Figure 9. MII Reception Cycle Timing-2 ..................................................................................................26
Figure 10. SNI Transmission Cycle Timing-1 ............................................................................................27
Figure 11. SNI Transmission Cycle Timing-2 ............................................................................................27
Figure 12. SNI Reception Cycle Timing-1..................................................................................................28
Figure 13. SNI Reception Cycle Timing-2..................................................................................................28
Figure 14. MDC/MDIO Timing ..................................................................................................................29
Figure 15. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................29
Figure 16. MDC/MDIO PHY to MAC Reception Without Error ...............................................................30
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
vi
Track ID: JATR-1076-21 Rev. 1.24

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部品番号部品説明メーカ
RTL8201CL-LF

SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER

Realtek
Realtek


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