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PDF RTL8201CL Data sheet ( Hoja de datos )
| Número de pieza | RTL8201CL | |
| Descripción | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER | |
| Fabricantes | Realtek | |
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RTL8201CL
RTL8201CL-LF
RTL8201CL-VD
RTL8201CL-VD-LF
SINGLE-CHIP/SINGLE-PORT
10/100M FAST ETHERNET PHYCEIVER
DATASHEET
Rev. 1.24
04 November 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
1 page  
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RTL8201CL
Datasheet
7.11. 3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT.......................................................................................22
7.12. FAR END FAULT INDICATION ......................................................................................................................................22
8. CHARACTERISTICS .......................................................................................................................................................23
8.1. DC CHARACTERISTICS...............................................................................................................................................23
8.1.1. Absolute Maximum Ratings ..................................................................................................................................23
8.1.2. Operating Conditions ...........................................................................................................................................23
8.1.3. Power Dissipation ................................................................................................................................................23
8.1.4. Input Voltage: Vcc ................................................................................................................................................23
8.2. AC CHARACTERISTICS...............................................................................................................................................24
8.2.1. MII Transmission Cycle Timing............................................................................................................................24
8.2.2. MII Reception Cycle Timing .................................................................................................................................25
8.2.3. SNI Transmission Cycle Timing............................................................................................................................27
8.2.4. SNI Reception Cycle Timing .................................................................................................................................28
8.2.5. MDC/MDIO Timing..............................................................................................................................................29
8.3. CRYSTAL CHARACTERISTICS ......................................................................................................................................30
8.4. TRANSFORMER CHARACTERISTICS ............................................................................................................................30
9. MECHANICAL DIMENSIONS .......................................................................................................................................31
9.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................32
10. ORDERING INFORMATION......................................................................................................................................33
List of Tables
Table 1. MII Interface..................................................................................................................................4
Table 2. SNI (Serial Network Interface) 10Mbps Only ..............................................................................5
Table 3. Clock Interface ..............................................................................................................................5
Table 4. 10Mbps/100Mbps Network Interface............................................................................................6
Table 5. Device Configuration Interface .....................................................................................................6
Table 6. LED Interface/PHY Address Configuration..................................................................................7
Table 7. Power and Ground Pins .................................................................................................................7
Table 8. Reset and Other Pins......................................................................................................................7
Table 9. Register 0 Basic Mode Control Register .......................................................................................8
Table 10. Register 1 Basic Mode Status Register..........................................................................................9
Table 11. Register 2 PHY Identifier Register 1.............................................................................................9
Table 12. Register 3 PHY Identifier Register 2.............................................................................................9
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)..................................................10
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) ....................................10
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) .........................................................11
Table 16. Register 16 NWay Setup Register (NSR)....................................................................................12
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) ..............................12
Table 18. Register 18 RX_ER Counter (REC)............................................................................................13
Table 19. Register 19 SNR Display Register ..............................................................................................13
Table 20. Register 25 Test Register.............................................................................................................13
Table 21. Serial Management ......................................................................................................................15
Table 22. Setting the Medium Type and Interface Mode to MAC..............................................................16
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
v
Track ID: JATR-1076-21 Rev. 1.24
5 Page 
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RTL8201CL
Datasheet
Name
RXER/
FXEN
Type
O/LI
MDC
I
MDIO
IO
Pin No.
24
25
26
Description
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid
symbol, this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is possible
to use an external 5.1KΩ pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be asynchronous
to the transmit TXC and receive RXC clocks. The clock rate can be up to
2.5MHz. An internal weak pull high resistor prevents the bus floating.
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
5.2. SNI (Serial Network Interface) 10Mbps Only
Name
COL
RXD0
CRS
RXC
TXD0
TXC
TXEN
Type
O
O
O
O
I
O
I
Table 2. SNI (Serial Network Interface) 10Mbps Only
Pin No. Description
1 Collision Detect.
21 Received Serial Data.
23 Carrier Sense.
16 Receive Clock.
Resolved from received data.
6 Transmit Serial Data.
7 Transmit Clock.
Generated by PHY.
2 Transmit Enable.
For MAC to indicate transmit operation.
5.3. Clock Interface
Name
X2
X1
Type
O
I
Pin No.
47
46
Table 3. Clock Interface
Description
25MHz Crystal Output.
This pin provides the 25MHz crystal output. It must be left open when an
external 25MHz oscillator drives X1.
25MHz Crystal Input.
This pin provides the 25MHz crystal input. If a 25MHz oscillator is used, connect
X1 to the oscillator’s output (see 8.3 Crystal Characteristics, page 30, for clock
source specifications.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
5
Track ID: JATR-1076-21 Rev. 1.24
11 Page | ||
| Páginas | Total 39 Páginas | |
| PDF Descargar | [ Datasheet RTL8201CL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| RTL8201CL | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER | Realtek |
| RTL8201CL-LF | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER | Realtek |
| RTL8201CL-VD | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER | Realtek |
| RTL8201CL-VD-LF | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER | Realtek |
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