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CY14V104NA の電気的特性と機能

CY14V104NAのメーカーはCypress Semiconductorです、この部品の機能は「4-Mbit (512 K x 8 / 256 K x 16) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14V104NA
部品説明 4-Mbit (512 K x 8 / 256 K x 16) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14V104NA Datasheet, CY14V104NA PDF,ピン配置, 機能
CY14V104LA
CY14V104NA
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Features
Functional Description
25 ns and 45 ns access times
Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16
(CY14V104NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and recall cycles
1-million STORE cycles to QuantumTrap
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
20 year data retention
Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V
Industrial temperature
48-ball fine-pitch ball grid array (FBGA) package
Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram [1, 2, 3]
Quatrum Trap
VCC VCCQ VCAP
2048 X 2048
A0 R
POWER
A1 O
STORE
CONTROL
A2
A3
A4
A5
W
RECALL
D
E STATIC RAM
STORE/RECALL
CONTROL
HSB
A6 C ARRAY
A7
A8
A17
O 2048 X 2048
D
E
SOFTWARE
DETECT
A14 - A2
A18 R
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A9 A10 A11 A12 A13 A14 A15 A16
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-53954 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 6, 2011
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CY14V104NA pdf, ピン配列
CY14V104LA
CY14V104NA
Pinouts
1
(× 8)
Top View
(not to scale)
2 34 5
Figure 1. Pin Diagram – 48-ball FBGA
(× 16)
Top View
(not to scale)
6 12 34 5
6
NC OE A0 A1 A2 VCC
NC NC A3 A4 CE NC
DQ0 NC A5
A6 NC DQ4
VSS DQ1 A17 A7 DQ5 VCCQ
VCCQ DQ2 VCAP A16 DQ6 VSS
DQ3 NC A14 A15 NC DQ7
NC HSB A12 A13 WE NC
A18 A8 A9 A10 A11 NC [4]
A
B
C
D
E
F
G
H
BLE OE A0 A1 A2 VCC
DQ8 BHE A3
A4 CE DQ0
DQ9 DQ10 A5
A6 DQ1 DQ2
VSS DQ11 A17 A7 DQ3 VCCQ
VCCQ DQ12 VCAP A16 DQ4 VSS
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 HSB A12 A13 WE DQ7
NC[4] A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
Pin Definitions
Pin Name I/O Type
Description
A0–A18 Input
A0–A17
DQ0–DQ7 Input/output
DQ0–DQ15
WE Input
Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for × 8 Configuration.
Address Inputs Used to Select One of the 262,144 words of the nvSRAM for × 16 Configuration.
Bidirectional Data I/O Lines for × 8 Configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for × 16 Configuration. Used as input or output lines depending on operation.
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE Input
OE Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
BHE
BLE
VSS
VCC
VCCQ
HSB
Input
Input
Ground
Byte High Enable, Active LOW. Controls DQ15–DQ8.
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Ground for the Device. Must be connected to the ground of the system.
Power supply Power Supply Inputs to the Core of the Device.
Power supply Power Supply Inputs for the Inputs and Outputs of the Device.
Input/output
Hardware Store Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection
optional).
VCAP Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
NC No Connect No Connect. This pin is not connected to the die.
Note
4. Address expansion for 8-Mbit. NC pin not connected to die.
Document #: 001-53954 Rev. *F
Page 3 of 22
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CY14V104NA 電子部品, 半導体
CY14V104LA
CY14V104NA
Table 1. Mode Selection (continued)
CE
WE
OE
BHE, BLE[5]
A15–A0[6]
Mode
I/O
Power
L
H
L
X
0x4E38
Read SRAM Output Data
Active[8]
0xB1C7
Read SRAM Output Data
0x83E0
Read SRAM Output Data
0x7C1F
Read SRAM Output Data
0x703F
Read SRAM Output Data
0x4B46
AutoStore Output Data
Enable
L
H
L
X
0x4E38
Read SRAM Output Data Active ICC2[8]
0xB1C7
Read SRAM Output Data
0x83E0
Read SRAM Output Data
0x7C1F
Read SRAM Output Data
0x703F
Read SRAM Output Data
0x8FC0
Non-volatile Output High Z
Store
L
H
L
X
0x4E38
Read SRAM Output Data
Active[8]
0xB1C7
Read SRAM Output Data
0x83E0
Read SRAM Output Data
0x7C1F
Read SRAM Output Data
0x703F
Read SRAM Output Data
0x4C63
Non-volatile Output High Z
Recall
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled.
Data Protection
The CY14V104LA/CY14V104NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the
CY14V104LA/CY14V104NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). When VCCQ < VIODIS, I/Os are disabled (no STORE
takes place). This protects against inadvertent writes during
brown out conditions on VCCQ supply.
Noise Considerations
Refer to Cypress application note, AN1064.
Note
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53954 Rev. *F
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部品番号部品説明メーカ
CY14V104NA

4-Mbit (512 K x 8 / 256 K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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