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CY14E512J の電気的特性と機能

CY14E512JのメーカーはCypress Semiconductorです、この部品の機能は「512-Kbit (64 K x 8) Serial (I2C) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14E512J
部品説明 512-Kbit (64 K x 8) Serial (I2C) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14E512J Datasheet, CY14E512J PDF,ピン配置, 機能
CY14C512J
CY14B512J, CY14E512J
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14X512J1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
High speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast-mode Plus: 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one-quarter, one-half, or entire
array
I2C access to special functions
Nonvolatile STORE/RECALL
8 byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 150 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C512J: VCC = 2.4 V to 2.6 V
• CY14B512J: VCC = 2.7 V to 3.6 V
• CY14E512J: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C512J/CY14B512J/CY14E512J combines a
512-Kbit nvSRAM[1] with a nonvolatile element in each memory
cell. The memory is organized as 64 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X512J1). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through I2C commands.
Configuration
Feature
CY14X512J1 CY14X512J2 CY14X512J3
AutoStore
No Yes Yes
Software STORE
Yes
Yes
Yes
Hardware STORE
No
No Yes
Slave Address pins A2, A1, A0
A2, A1
A2, A1, A0
Logic Block Diagram
VCC VCAP
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
Note
1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Quantrum Trap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-65232 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 4, 2011
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CY14E512J pdf, ピン配列
CY14C512J
CY14B512J, CY14E512J
Pinouts
Figure 1. Pin Diagram – 8-pin SOIC
A0 1
8
A1 2 CY14X512J1 7
A2
3
Top View 6
not to scale
VSS 4
5
VCC
WP
SCL
SDA
VCAP
A1
A2
VSS
18
2 CY14X512J2
Top View
3 not to scale
4
7
6
5
VCC
WP
SCL
SDA
Figure 2. Pin Diagram – 16-pin SOIC
NC 1
16 VCC
NC 2
15 NC
NC 3 CY14X512J3 14 VCAP
NC 4
WP 5
Top View 13
not to scale
12
A2
SDA
A0 6
11 SCL
NC
VSS
7
8
10 A1
9 HSB
Pin Definitions
Pin Name
SCL
SDA
WP
A2-A0[2]
HSB
VCAP
NC
VSS
VCC
I/O Type
Input
Input/Output
Input
Input
Input/Output
Power Supply
No connect
Power supply
Power supply
Description
Clock. Runs at speeds up to a maximum of fSCL.
I/O. Input/Output of data through I2C interface.
Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can
be left open if not connected.
Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can
be left open if not connected.
Hardware STORE Busy
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no
connect. It must never be connected to ground.
No connect. This pin is not connected to the die.
Ground.
Power supply.
Note
2. A0 pin is not available in CY14X512J2.
Document #: 001-65232 Rev. *B
Page 3 of 31
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CY14E512J 電子部品, 半導体
CY14C512J
CY14B512J, CY14E512J
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Figure 6. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
not acknowledge (A)
acknowledge (A)
SCL FROM
MASTER
S
START
condition
1
2
89
clock pulse for
acknowledgement
High Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device into high speed mode. This enables master slave
communication for speed upto 3.4 MHz. A stop condition exits
Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
F/S-mode
Hs-mode
F/S-mode
S MASTER CODE A Sr SLAVE ADD. R/W A
DATA
A/A P
n (bytes+ack.)
Hs-mode continues
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
Sr SLAVE ADD.
continue data transfer in Hs-mode, the master sends Repeated
START (Sr). See Figure 13 on page 11 and
Figure 16 on page 12 for Hs-mode timings for read and write
operation.
Document #: 001-65232 Rev. *B
Page 6 of 31
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共有リンク

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部品番号部品説明メーカ
CY14E512I

512-Kbit (64 K x 8) Serial (I2C) nvSRAM

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CY14E512J

512-Kbit (64 K x 8) Serial (I2C) nvSRAM

Cypress Semiconductor
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CY14E512PA

512-Kbit (64 K x 8) SPI nvSRAM

Cypress Semiconductor
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CY14E512Q

512-Kbit (64 K x 8) SPI nvSRAM

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