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CY14B108M の電気的特性と機能

CY14B108MのメーカーはCypress Semiconductorです、この部品の機能は「8-Mbit (1024 K x 8/512 K x 16) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14B108M
部品説明 8-Mbit (1024 K x 8/512 K x 16) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14B108M Datasheet, CY14B108M PDF,ピン配置, 機能
CY14B108K, CY14B108M
8-Mbit (1024 K × 8/512 K × 16) nvSRAM
with Real Time Clock
8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock
Features
25 ns and 45 ns access times
Internally organized as 1024 K × 8 (CY14B108K) or 512 K × 16
(CY14B108M)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite Read, Write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20%, –10% operation
Data integrity of Cypress nonvolatile static RAM (nvSRAM)
combined with full-featured real time clock (RTC)
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Industrial temperature
44 and 54-pin thin small outline package (TSOP) Type II
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B108K/CY14B108M combines a 8-Mbit
nonvolatile static RAM (nvSRAM) with a full featured RTC in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-47378 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 13, 2011
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CY14B108M pdf, ピン配列
CY14B108K, CY14B108M
Contents
Pinouts .............................................................................. 4
Pin Definitions .................................................................. 5
Device Operation .............................................................. 6
SRAM Read ....................................................................... 6
SRAM Write ....................................................................... 6
AutoStore Operation ........................................................ 6
Hardware STORE (HSB) Operation ................................. 7
Hardware RECALL (Power-Up) ....................................... 7
Software STORE ............................................................... 7
Software RECALL ............................................................. 7
Preventing AutoStore ....................................................... 8
Data Protection ................................................................. 9
Noise Considerations ....................................................... 9
Real Time Clock Operation .............................................. 9
nvTime Operation ........................................................ 9
Clock Operations ......................................................... 9
Reading the Clock ....................................................... 9
Setting the Clock ......................................................... 9
Backup Power ............................................................. 9
Stopping and Starting the Oscillator .......................... 10
Calibrating the Clock ................................................. 10
Alarm ......................................................................... 10
Watchdog Timer ........................................................ 10
Power Monitor ........................................................... 11
Interrupts ................................................................... 11
Flags Register ........................................................... 12
Best Practices ................................................................. 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
DC Electrical Characteristics ........................................ 18
Data Retention and Endurance ..................................... 19
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads ................................................................ 19
AC Test Conditions ........................................................ 19
RTC Characteristics ....................................................... 20
AC Switching Characteristics ....................................... 21
Switching Waveforms .................................................... 21
AutoStore/Power-Up RECALL ....................................... 24
Switching Waveforms .................................................... 24
Software Controlled STORE and RECALL Cycle ........ 25
Switching Waveforms .................................................... 25
Hardware STORE Cycle ................................................. 26
Switching Waveforms .................................................... 26
Truth Table For SRAM Operations ................................ 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Document #: 001-47378 Rev. *G
Page 3 of 33
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CY14B108M 電子部品, 半導体
CY14B108K, CY14B108M
Device Operation
The CY14B108K/CY14B108M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B108K/CY14B108M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 27
for a complete description of read and write modes.
SRAM Read
The CY14B108K/CY14B108M performs a read cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A0–19 or A0–18 determines which of the
1,048,576 data bytes or 524,288 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DO0–15
are written into the memory if it is valid for tSD time before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B108K/CY14B108M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device
power-down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B108K/CY14B108M.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2. AutoStore Mode
CC
0.1 uF
VCC
WE
VCAP
VSS
VCAP
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 18 for the size of the VCAP. The voltage
on the VCAP pin is driven to VCC by a regulator on the chip. A
pull-up should be placed on WE to hold it inactive during
power-up. This pull-up is effective only if the WE signal is tristate
during power-up. Many MPUs tristate their controls on power-up.
This should be verified when using the pull-up. When the
nvSRAM comes out of power-on-RECALL, the MPU must be
active or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore, and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Document #: 001-47378 Rev. *G
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共有リンク

Link :


部品番号部品説明メーカ
CY14B108K

8-Mbit (1024 K x 8/512 K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B108L

8-Mbit (1024 K x 8/512 K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B108M

8-Mbit (1024 K x 8/512 K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B108N

8-Mbit (1024 K x 8/512 K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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