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PDF CY14B108K Data sheet ( Hoja de datos )
| Número de pieza | CY14B108K | |
| Descripción | 8-Mbit (1024 K x 8/512 K x 16) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY14B108K, CY14B108M
8-Mbit (1024 K × 8/512 K × 16) nvSRAM
with Real Time Clock
8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock
Features
■ 25 ns and 45 ns access times
■ Internally organized as 1024 K × 8 (CY14B108K) or 512 K × 16
(CY14B108M)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ High reliability
■ Infinite Read, Write, and RECALL cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20%, –10% operation
■ Data integrity of Cypress nonvolatile static RAM (nvSRAM)
combined with full-featured real time clock (RTC)
■ Watchdog timer
■ Clock alarm with programmable interrupts
■ Capacitor or battery backup for RTC
■ Industrial temperature
■ 44 and 54-pin thin small outline package (TSOP) Type II
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B108K/CY14B108M combines a 8-Mbit
nonvolatile static RAM (nvSRAM) with a full featured RTC in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-47378 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 13, 2011
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CY14B108K, CY14B108M
Pin Definitions
Pin Name I/O Type
Description
A0–A19
A0–A18
DQ0–DQ7
DQ0–DQ15
NC
Input Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration.
Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
No connect No connects. This pin is not connected to the die.
WE
Input
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
BHE
BLE
Xout
Xin
VRTCcap
VRTCbat
INT
Input
Input
Output
Byte High Enable, Active LOW. Controls DQ15–DQ8.
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Crystal connection. Drives crystal on start up.
Input Crystal connection. For 32.768 kHz crystal.
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.
Power supply Battery supplied Backup RTC supply voltage. Left unconnected if VRTCcap is used.
Output Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
VCC
HSB
Ground Ground for the device. Must be connected to ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%.
Input/Output Hardware STORE Busy (HSB).When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Document #: 001-47378 Rev. *G
Page 5 of 33
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CY14B108K, CY14B108M
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5–D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 3. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the watchdog interrupt
enable (WIE) bit in the interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the flags registers.
Figure 3. Watchdog Timer Block Diagram
Oscillator
32,768 KHz
Clock
Divider
32 Hz
Counter
1 Hz
Zero
Compare
WDF
WDS
Load
Register
WDW
DQ
Q
write to
Watchdog
Register
.
Power Monitor
Watchdog
Register
The CY14B108K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
As described in the section AutoStore Operation on page 6,
when VSWITCH is reached as VCC decays from power loss, a data
STORE operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, read and write
operations to nvSRAM are inhibited and the RTC functions are
not available to the user. The RTC clock continues to operate in
the background. The updated RTC time keeping registers data
are available to the user after VCC is restored to the device (see
AutoStore/Power-Up RECALL on page 24).
Interrupts
The CY14B108K has flags register, interrupt register, and
interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0xFFFF6). In addition, each has an associated flag bit
in the flags register (0xFFFF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
Note CY14B108K generates valid interrupts only after the
Power-up RECALL sequence is completed. All events on INT pin
must be ignored for tHRECALL duration after powerup.
Interrupt Register
Watchdog Interrupt Enable (WIE). When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in flags register.
Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flags register.
Power Fail Interrupt Enable (PFE). When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in flags
register.
High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives HIGH only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10 k resistor while using the
interrupt in active LOW mode.
Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the flags register is read. If the INT pin is used as a
host reset, the flags register is not read during a reset.
Document #: 001-47378 Rev. *G
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| PDF Descargar | [ Datasheet CY14B108K.PDF ] | |
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