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CY14E256I の電気的特性と機能

CY14E256IのメーカーはCypress Semiconductorです、この部品の機能は「256-Kbit (32 K x 8) Serial (I2C) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14E256I
部品説明 256-Kbit (32 K x 8) Serial (I2C) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14E256I Datasheet, CY14E256I PDF,ピン配置, 機能
CY14C256I
CY14B256I, CY14E256I
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
with Real Time Clock
256-Kbit (32 K × 8) Serial (I2C) nvSRAM with Real Time Clock
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL
RECALL)
to
or
SRAM initiated on power-up (Power-Up
by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real Time Clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 µA (typical)
High-speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast mode Plus 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one-quarter, one-half, or entire
array
I2C access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 250 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C256I : VCC = 2.4 V to 2.6 V
• CY14B256I : VCC = 2.7 V to 3.6 V
• CY14E256I : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C256I/CY14B256I/CY14E256I combines a
256-Kbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
QuantrumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
X in RTC Control Logic
INT/SQW
Registers
Xout Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-65230 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 5, 2011
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CY14E256I pdf, ピン配列
CY14C256I
CY14B256I, CY14E256I
Pinouts
Figure 1. Pin Diagram - 16-pin SOIC
NC
VRTCbat
Xout
Xin
1
2
3
4
WP
A0
VRTCcap
VSS
5
6
7
8
16 VCC
15 INT/SQW
Top View
not to scale
14
13
12
VCAP
A2
SDA
11 SCL
10 A1
9 HSB
Pin Definitions
Pin Name
SCL
SDA
WP
A2-A0
HSB
VCAP
VRTCcap
VRTCbat
Xout
Xin
INT/SQW
NC
VSS
VCC
I/O Type
Input
Input/Output
Input
Input
Input/Output
Power supply
Power supply
Power supply
Output
Input
Output
No connect
Power supply
Power supply
Description
Clock: Runs at speeds up to a maximum of fSCL.
I/O: Input/Output of data through I2C interface.
Write Protect: Protects the memory from all writes. This pin is internally pulled LOW and hence can
be left open if not connected.
Slave Address: Defines the slave address for I2C. These pins are internally pulled LOW and hence
can be left open if not connected.
Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore Capacitor: Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as No
Connect. It must never be connected to ground.
Capacitor Backup for RTC: Left unconnected if VRTCbat is used.
Battery Backup for RTC: Left unconnected if VRTCcap is used.
Crystal output connection
Crystal input connection
Interrupt Output/Calibration/Square Wave. Programmable to respond to the clock alarm, the
watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or
LOW (open drain). In Calibration mode, a 512 Hz square wave is driven out. In Square Wave mode,
the user may select a frequency of 1 Hz, 512 Hz, 4096 Hz, or 32768 Hz to be used as a continuous
output.
No connect. This pin is not connected to the die.
Ground
Power supply
Document #: 001-65230 Rev. *B
Page 3 of 41
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CY14E256I 電子部品, 半導体
CY14C256I
CY14B256I, CY14E256I
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
Not acknowledge (A)
Acknowledge (A)
SCL FROM
MASTER
S
START
Condition
1
2
89
Clock pulse for
acknowledgement
High-Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device in high-speed mode. This enables master/slave
communication for speeds up to 3.4 MHz. A stop condition will
exit Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
continue data transfer in Hs-mode, the master sends Repeated
START (Sr).
See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode
timings for read and write operation.
Figure 6. Data Transfer Format in Hs-mode
handbook, full pagewidth
F/S-mode
Hs-mode
F/S-mode
S MASTER CODE A Sr SLAVE ADD. R/W A
DATA
A/A P
n (bytes+ack.)
Hs-mode continues
Sr SLAVE ADD.
Document #: 001-65230 Rev. *B
Page 6 of 41
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共有リンク

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