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HD74LV1GT125A の電気的特性と機能

HD74LV1GT125AのメーカーはRenesas Technologyです、この部品の機能は「Bus Buffer Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD74LV1GT125A
部品説明 Bus Buffer Gate
メーカ Renesas Technology
ロゴ Renesas Technology ロゴ 




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HD74LV1GT125A Datasheet, HD74LV1GT125A PDF,ピン配置, 機能
HD74LV1GT125A
Bus Buffer Gate with 3–state Output /
CMOS Logic Level Shifter
www.DataSheet4U.net
Description
REJ03D0123-0900
Rev.9.00
Mar 21, 2008
The HD74LV1GT125A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the
associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE
should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current
sourcing capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the
input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from
1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-
speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
HD74LV1GT125ACME CMPAK–5 pin
PTSP0005ZC-A
(CMPAK-5V)
HD74LV1GT125AVSE
VSON–5 pin
PUSN0005KA-A
(TNP-5DV)
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
CM
VS
Taping Abbreviation
(Quantity)
E (3000 pcs/reel)
E (3000 pcs/reel)
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 1 of 7

1 Page





HD74LV1GT125A pdf, ピン配列
HD74LV1GT125A
Pin Arrangement
OE 1
A2
GND 3
5 VCC
4Y
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
VCC
VI
VO
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
Output : H or L
V
VCC : OFF or Output : Z
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg –65 to 150 °C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two
of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Supply voltage range
VCC 3.0
Input voltage range
VI 0
Output voltage range
0
VO 0
Output current
IOH
IOL
Input transition rise or fall rate
t / v
0
0
Operating free-air temperature
Ta
–40
Note: Unused or floating inputs must be held high or low.
Max
5.5
5.5
VCC
5.5
6
12
–6
–12
100
20
85
Unit
V
V
V
mA
mA
ns / V
°C
Conditions
Output : Z
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 3 of 7


3Pages


HD74LV1GT125A 電子部品, 半導体
HD74LV1GT125A
Waveforms
• Waveforms – 1
tr
Input A
10 %
90 %
Vref
tPLH
tf
90 %
Vref
10 %
tPHL
Output Y
50%
50%
VI
GND
VOH
VOL
• Waveforms – 2
tf
Input OE
90 %
Vref
10 %
tZL
Waveform – A
50%
tZH
Waveform – B
50%
tr
10 %
90 %
Vref
tLZ
tHZ
VOL + 0.3 V
VOH – 0.3 V
VI
GND
VCC
VOL
VOH
GND
VCC (V)
INPUTS
VI tr / tf
Vref
3.3±0.3 2.5 V 3.0 ns 50%
5.0±0.5 3 V 3.0 ns 1.5 V
Notes: 1. Input waveform : PRR 1 MHz, Zo = 50 Ω.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 6 of 7

6 Page



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部品番号部品説明メーカ
HD74LV1GT125A

Bus Buffer Gate

Renesas Technology
Renesas Technology


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