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PDF MV3506 Data sheet ( Hoja de datos )
| Número de pieza | MV3506 | |
| Descripción | (MV3506 - MV3508) FILTER/CODEC | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
1 page  
MV3506/7/8
PIN DESCRIPTIONS
Symbol
TST/SE
Pin No..
3506/7/8
1
CLK SEL
2
T SHIFT
SYS CLK
3
4
T STROBE
5
PCM OUT
6
D GND
CAZ
7
8
R SHIFT
9
R STROBE
10
PCM IN
VSS
A GND
4
11
12
13
Pin name and description
Test/Squelch Enable (Intemal Connection/Digital Input). This pin is an internal
test connection on the MV3506, MV3507 and it is the squelch
enable input on the MV3508.
On the MV3506/7 it should be left unconnected or connected to the A GND pin
via a capacitor for normal operation.
On the MV3508 it should be tied high to enable the squelch feature and it should
be left unconnected otherwise.
Clock Select (Three Level Input). This pin selects the proper divide ratios for a
256kHz, 1.544MHz or 2.048MHz system clock. The pin is tied to VDD (+5V) for
2.048MHz operation, to D GND (0V) for 256kHz operation, and to VSS (-5V) for
1.544MHz operation.
Transmit Shift Clock (Digital Input). This TTL compatible input shifts PCM data
out of the coder on the positive going edges after receiving a positive edge on the
T STROBE input. The clocking rate can vary from 64kHz to 2.048MHz.
System Clock (Digital Input). This pin is a TTL compatible input for either a
256kHz, 1.544MHz or a 2.048MHz clock that is divided down to provide the filter
clocks. The status of the CLK SEL pin must correspond to the provided clock
frequency.
Transmit Strobe (Digital Input with Pull-up). This TTL compatible pulse input
(typically 8kHz) is used for analog sampling and initiating the PCM output from the
coder. It must be synchronised with the T SHIFT and SYS CLK clocks with its
positive going edges occurring after the falling edges of these clocks. The width of
this signal is not critical. An internal bit counter generates the necessary timing for
PCM output.
PCM Out (Pull-down Output). This is a LS TTL compatible open-drain output. It is
active only during transmission of PCM output for 8-bit periods of the T SHIFT
clock signal following positive edge on the T STROBE input. Data is clocked out
by the positive edge on the T SHIFT clock into one 510Ω pull-up per system plus 2
LS TTL inputs.
Digital Ground (Power Input). 0V.
Auto Zero Capacitor (Reterence Node). A capacitor of 0.1µF (±20%) should be
connected between this pin and CAZ GND for coder auto zero operation. The sign bit
of the PCM data is integrated and fed back to the comparator for DC offset
cancellation.
Receive Shift Clock (Digital Input). This TTL compatible input shifts PCM data into
the decoder on the negative going edges after receiving a positive edge on the
R STROBE input. The clocking rate can vary from 64kHz to 2.048MHz.
Receive Strobe (Digital Input with Pull-up). This TTL compatible pulse input
(typically 8kHz) initiates clocking of PCM input data into the decoder. It must be
synchronised with the R SHIFT and SYS CLK clocks with its positive going edges
occurring after the falling edges of these clocks. The width of the signal is not
critical. An internal bit counter generates necessary timing for PCM input.
PCM In (Digital Input). This is a TTL compatible input for supplying PCM input
data to the decoder. Data is clocked in by the negative edge of the R SHIFT clock.
Negative Supply (Power Input). -5V.
Analog Ground (Reference Node). This is the ground reference node for analog
signals.
5 Page 
MV3506/7/8
DIGITAL SWITCHING CHARACTERISTICS - TRANSMIT DATA (SEE FIG.13)
Characteristic
Symbol Min
Value
Typ (1) | Max
PCM output holt time
PCM output delay
tPOH
tPOD
0
50
100 150
Units
ns
ns
Conditions
2.0V
T STROBE
0.8V
2.0V
T SHIFT
0.8V
2.0V
PCM OUT
0.8V
tPOD
BIT 1
tPOD
BITS 2 TO 7
tPOD
BIT 8
tPOD
tPOH
tPOH
tPOH
Figure 13: Timing - transmit data
ANALOG CHANNEL CHARACTERISTICS - FILTER DELAYS
Characteristic
Symbol Min
Value
Typ.(1)
Max.
tPOH
Units
Conditions
Transmit filter delay
Receive filter delay
tTFD
tRFD
182 µs 1kHz
110 µs 1kHz
ANALOG CHANNEL CHARACTERISTICS - A-LAW
Characteristic
0dBm0 level (see Note 2)
Variation in 0dBm0 level
Weighted idle channel noise
Symbol
Min.
0dBM0
∆0dBm0
ICNW
5.3
-0.3
Single frequency
idle channel noise
Weighted receive
idle channel noise
Spurious out-band noise
Spurious in-band noise
Two tone interdemodulation
Tone + power inter-
demodulation
Crosstalk attenuation between
VIN and VOUT
ICNSF
ICNWR
NSOB
NSIB
IMD2T
IMDTP
Ax 75
10
Value
Typ. (1)
5.8
0
-85
Max.
6.3
0.3
-73
-60
-78
-30
-40
-35
-49
80
Units
Conditions
dBm
dB
dBm0p
dBm0
dBm0p
dBm0
dBm0
dBm0
dBm0
dB
±5V, 25°C
Over test conditions
CCITT G.712, §5.1
(see Note 3)
CCITT G.712, §5.2
CCITT G.712, §5.3
CCITT G.712, §7.1
CCITT G.712, §10
CCITT G.712, §8.1
CCITT G.712, §8.2
CCITT G.712, §12
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MV3506.PDF ] | |
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