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ADP5042 の電気的特性と機能

ADP5042のメーカーはAnalog Devicesです、この部品の機能は「Micro PMU」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADP5042
部品説明 Micro PMU
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADP5042 Datasheet, ADP5042 PDF,ピン配置, 機能
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Micro PMU with 0.8 A Buck, Two 300 mA LDOs
Supervisory, Watchdog and Manual Reset
ADP5042
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 0.8 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to VCC = 1 V
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck key specifications
Current mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Low VIN from 1.7 V to 5.5 V
Stable with1 μF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise
110 μV rms typical output noise at VOUT = 2.8 V
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes the
board space.
The MODE pin selects the buck mode of operation. When set
to logic high, the buck regulators operate in forced PWM mode.
When the MODE pin is set to logic low, the buck regulators
operate in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
HIGH LEVEL BLOCK DIAGRAM
RFILT = 30
VIN1 = 2.3V
TO 5.5V
C5
4.7µF
AVIN
VIN1
ON
OFF
EN1
VIN2 = 1.7V
TO 5.5V
C1
1µF
VIN2
ON
OFF
EN2
AVIN
BUCK
EN_BK
LDO1
(DIGITAL)
EN_LDO1
AVIN
VIN3 = 1.7V
TO 5.5V
C3
1µF
ON
OFF
MR
EN3
VIN3
EN_LDO2
LDO2
(ANALOG)
AGND
SW
VOUT1
PGND
L1
1µH
VOUT1 AT
C6 800mA
10µF
MODE
VOUT2
WSTAT
nRSTO
FPWM
PSM/PWM
VOUT2 AT
300mA
C2
1µF
WDI1
WDI2
VOUT3
VOUT3 AT
300mA
C4
1µF
Figure 1.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5042 LDOs extend the battery life of
portable devices. The two LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5042 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5042 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. They also provide power-on
reset signals. An on-chip dual watchdog timer can reset the
microprocessor or power cycle the system (Watchdog 2) if it
fails to strobe within a preset timeout period.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.

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ADP5042 pdf, ピン配列
ADP5042
SPECIFICATIONS
GENERAL SPECIFICATION
AVIN, VIN1 = (VOUT1+ 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, VIN3, TA = 25°C, unless otherwise noted. Regulators
are enabled.
Table 1.
Parameter
AVIN UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
SHUTDOWN CURRENT
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
ENx, WDIx, MODE, WMOD, MR INPUTS
Input Logic High
Input Logic Low
Input Leakage Current (WMOD
Excluded)
WMOD Input Leakage Current
OPEN-DRAIN OUTPUTS
nRSTO, WSTAT Output Voltage
Open-Drain Reset Output Leakage
Current
Symbol
UVLOAVIN
UVLOAVINRISE
UVLOAVINFALL
IGND-SD
TSSD
TSSD-HYS
VIH
VIL
VI-LEAKAGE
VI-LKG-WMOD
VOL
Description
TJ = −40°C to +125°C
ENx = GND
ENx = GND, TJ = −40°C to +125°C
TJ rising
2.5 V ≤ AVIN ≤ 5.5 V
2.5 V ≤ AVIN ≤ 5.5 V
ENx = AVIN or GND
ENx = AVIN or GND, TJ = −40°C to +125°C
VWMOD = 3.6 V, TJ = −40°C to +125°C
AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA
Min Typ Max Unit
2.25 V
1.95 V
0.1 μA
2 μA
150 °C
20 °C
1.2 V
0.4 V
0.05 μA
1 μA
50 μA
30
1
mV
μA
SUPERVISORY SPECIFICATION
AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
SUPPLY
Supply Current (Supervisory Circuit Only)
RESET THRESHOLD ACCURACY
Min
VTH − 0.8%
VTH − 1.5%
Typ
45
43
VTH
VTH
Max Unit
55
52
VTH + 0.8%
VTH + 1.5%
μA
μA
V
V
RESET THRESHOLD TO OUTPUT DELAY
GLITCH IMMUNITY (tUOD)
RESET TIMEOUT PERIOD WATCHDOG1 (tRP1)
Option A
Option B
RESET TIMEOUT PERIOD WATCHDOG2 (tRP2)
VCC TO RESET DELAY (tRD)
REGULATORS SEQUENCING DELAY (tD1, tD2)
WATCHDOG INPUTS
Watchdog 1 Timeout Period (tWD1)
Option A
Option B
50
24
160
3.5
81.6
1.28
125 400
30 36
200 240
57
150
2
μs
ms
ms
ms
μs
ms
102
122.4
ms
1.6 1.92 sec
Test Conditions/Comments
AVIN = 5.5 V, EN1 = EN2 = EN3 = VIN
AVIN = 3.6 V, EN1 = EN2 = EN3 = VIN
TA = 25°C, sensed on VOUTx
TJ = −40°C to +125°C, sensed on
VOUTx
VTH = VUOT − 50 mV
VIN1 falling at 1 mV/μs
Rev. 0 | Page 3 of 32


3Pages


ADP5042 電子部品, 半導体
ADP5042
Parameter
Load Regulation1
DROPOUT VOLTAGE2
ACTIVE PULL-DOWN
START-UP TIME
CURRENT-LIMIT THRESHOLD3
OUTPUT NOISE
POWER SUPPLY REJECTION RATIO
Symbol
∆VOUT2/∆IOUT2
∆VOUT3/∆IOUT3
VDROPOUT
RPDLDO
TSTART-UP
ILIMIT
OUTLDO2NOISE
OUTLDO1NOISE
PSRR
Conditions
IOUT2, VOUT3 = 1 mA to 200 mA
Min
IOUT2, VOUT3 = 1 mA to 200 mA
TJ = −40°C to +125°C
VOUT2, VOUT3 = 3.3 V
IOUT2, IOUT3 = 10 mA
IOUT2, IOUT3 = 10 mA, TJ = −40°C to +125°C
IOUT2, IOUT3 = 200 mA
IOUT2, IOUT3 = 200 mA, TJ = −40°C to +125°C
EN2/EN3 = 0 V
VOUT2, VOUT3 = 3.3 V
TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V
1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, OUT3 = 2.8 V,
IOUT = 100 mA
100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
335
Typ Max
0.002
Unit
%/mA
0.0075 %/mA
4
5
60
100
600
85
470
123
110
59
140
129
66
66
57
60
mV
mV
mV
mV
Ω
μs
mA
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
dB
dB
dB
1 Based on an end-point calculation using 1 mA and 100 mA loads.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter
MINIMUM OUTPUT CAPACITANCE (BUCK)1
MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO1, LDO2)
CAPACITOR ESR
Symbol
CMIN1
CMIN23
RESR
Conditions
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
Min Typ Max Unit
7 40 μF
0.70 μF
0.001
1 The minimum output capacitance should be greater than 4.7 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met.
2 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.
Rev. 0 | Page 6 of 32

6 Page



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