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ADM1168 の電気的特性と機能

ADM1168のメーカーはAnalog Devicesです、この部品の機能は「Super Sequencer and Monitor」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADM1168
部品説明 Super Sequencer and Monitor
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADM1168 Datasheet, ADM1168 PDF,ピン配置, 機能
Data Sheet
Super Sequencer and Monitor with
Nonvolatile Fault Recording
ADM1168
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
16 event deep black box nonvolatile fault recording
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
NFET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1168
VREF
SMBus
INTERFACE
FAULT RECORDING EEPROM
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
VDDCAP
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF NFET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDOGND
VCCP GND
Figure 1.
GENERAL DESCRIPTION
The ADM1168 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems.
The device also provides up to eight programmable inputs
for monitoring undervoltage faults, overvoltage faults, or
out-of-window faults on up to eight supplies. In addition, eight
programmable outputs can be used as logic enables. Six of these
programmable outputs can also provide up to a 12 V output for
driving the gate of an NFET that can be placed in the path of a
supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs based
on the condition of the inputs.
A block of nonvolatile EEPROM is available that can be used to
store user-defined information and may also be used to hold a
number of fault records that are written by the sequencing engine
defined by the user when a particular fault or sequence occurs.
The ADM1168 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
For more information about the ADM1168 register map, refer
to the AN-721 Application Note.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADM1168 pdf, ピン配列
ADM1168
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Detailed Block Diagram .................................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Powering the ADM1168 ................................................................ 10
Slew Rate Consideration............................................................ 10
Inputs................................................................................................ 11
Supply Supervision..................................................................... 11
Programming the Supply Fault Detectors............................... 11
Input Comparator Hysteresis.................................................... 12
Input Glitch Filtering ................................................................. 12
Supply Supervision with VXx Inputs....................................... 13
VXx Pins as Digital Inputs ........................................................ 13
Outputs ............................................................................................ 14
Supply Sequencing Through Configurable Output Drivers.......14
REVISION HISTORY
1/15—Rev. A to Rev. B
Added Slew Rate Consideration Section ..................................... 10
8/13—Rev. 0 to Rev. A
Changed REVID Value from 0x12 to 0x10 in Table 10 ............. 22
4/11—Revision 0: Initial Version
Data Sheet
Default Output Configuration.................................................. 14
Sequencing Engine ......................................................................... 15
Overview ..................................................................................... 15
Warnings...................................................................................... 15
SMBus Jump (Unconditional Jump)........................................ 15
Sequencing Engine Application Example ............................... 16
Fault and Status Reporting........................................................ 17
Nonvolatile Black Box Fault Recording................................... 17
Black Box Writes with No External Supply ............................ 18
Applications Diagram .................................................................... 19
Communicating with the ADM1168........................................... 20
Configuration Download at Power-Up................................... 20
Updating the Configuration ..................................................... 20
Updating the Sequencing Engine............................................. 21
Internal Registers........................................................................ 21
EEPROM ..................................................................................... 21
Serial Bus Interface..................................................................... 22
SMBus Protocols for RAM and EEPROM.............................. 24
Write Operations ........................................................................ 24
Read Operations......................................................................... 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
Rev. B | Page 2 of 27


3Pages


ADM1168 電子部品, 半導体
Data Sheet
ADM1168
Parameter
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDO1 to PDO8)
VOH
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Stop Setup Time, tSU;STO
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
Min Typ Max Unit Test Conditions/Comments
500 kΩ
11 12.5 14 V IOH = 0 μA
10.5 12 13.5 V IOH = 1 μA
20 μA 2 V < VOH < 7 V
2.4
VPU − 0.3
0
16 20
90 100
V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V
VPU to VPx = 6.0 V, IOH = 0 mA
V VPU ≤ 2.7 V, IOH = 0.5 mA
0.50 V
IOL = 20 mA
20 mA Maximum sink current per PDO pin
60 mA Maximum total sink for all PDO pins
29 kΩ Internal pull-up
2 mA Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
10 μA VPDO = 14.4 V
110 kHz All on-chip time delays derived from this clock
2.0 V Maximum VIN = 5.5 V
0.8 V
Maximum VIN = 5.5 V
−1 μA VIN = 5.5 V
1 μA VIN = 0 V
5 pF
20 μA VDDCAP = 4.75 V, TA = 25°C, if known logic state is required
2.0 V
0.8 V
0.4 V
IOUT = −3.0 mA
See Figure 27
400 kHz
1.3 μs
0.6 μs
0.6 μs
0.6 μs
1.3 μs
0.6 μs
300 ns
300 ns
100 ns
250 ns
1 μA VIN = 0 V
10 μs
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
Rev. B | Page 5 of 27

6 Page



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