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71M6543G の電気的特性と機能

71M6543GのメーカーはTeridian Semiconductorです、この部品の機能は「Energy Meter ICs」です。


製品の詳細 ( Datasheet PDF )

部品番号 71M6543G
部品説明 Energy Meter ICs
メーカ Teridian Semiconductor
ロゴ Teridian Semiconductor ロゴ 




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71M6543G Datasheet, 71M6543G PDF,ピン配置, 機能
A Maxim Integrated Products Brand
19-5375; Rev 1.2; 4/11
71M6543F/H and 71M6543G/GH
Energy Meter ICs
DATA SHEET
April 2011
GENERAL DESCRIPTION
FEATURES
The 71M6543F, 71M6543H, 71M6543G, and 71M6543GH are
Teridian’s 4th-generation polyphase metering systems-on-chips
(SoCs) with a 5MHz 8051-compatible MPU core, low-power real-
time clock (RTC) with digital temperature compensation, flash
memory, and LCD driver. Our Single Converter Technology® with
a 22-bit delta-sigma ADC, seven analog inputs, digital metrology
temperature compensation, precision voltage reference, and a 32-
bit computation engine (CE) supports a wide range of metering
applications with very few external components.
The 71M6543F, 71M6543H, 71M6543G and 71M6543GH support
optional interfaces to the 71M6xx3 series of isolated sensors that
offer BOM cost reduction, immunity to magnetic tamper, and
enhanced reliability. The ICs feature ultra-low-power operation in
active and battery modes, 5KB shared RAM, and 64KB
(71M6543F, 71M6543H) or 128KB (71M6543G, 71M6543GH) of
flash memory, which can be programmed with code and/or data
during meter operation. High processing and sampling rates
combined with differential inputs offer a powerful metering platform
for commercial and industrial meters with up to class 0.2 accuracy
(71M6543H, 71M6543GH).
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
0.1% Accuracy Over 2000:1 Current Range
Exceeds IEC 62053/ANSI C12.20 Standards
Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
High-Speed Wh/VARh Pulse Outputs with
Programmable Width
64KB Flash, 5KB RAM (71M6543F/H)
128KB Flash, 5KB RAM (71M6543G/GH)
Up to Four Pulse Outputs with Pulse Count
Four-Quadrant Metering, Phase Sequencing
Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
Independent 32-Bit Compute Engine
46-64Hz Line Frequency Range with the Same
Calibration
Shunt Current Sensors
C
NEUTRAL
B
A
LOAD
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POWER SUPPLY
NEUTRAL
Note: This system is referenced to Neutral
3x TERIDIAN
71M6xx3
Pulse Transformers
AMR
IR
HOST
MUX and ADC
IADC0
IADC1
}IN*
VADC10 (VC)
IADC6
IADC7
}IC
VADC9 (VB)
IADC4
IADC5
}IB
VADC8 (VA)
IADC2
IADC3
}IA
V3P3A V3P3SYS GNDA GNDD
TERIDIAN
PWR MODE
CONTROL
71M6543F/ WAKE-UP
71M6543H/ REGULATOR
71M6543G/
VBAT
71M6543GH VBAT_RTC
TEMPERATURE BATTERY
SENSOR
MONITOR
VREF
SERIAL PORTS
TX
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
SPI INTERFACE
RAM
COMPUTE
ENGINE
FLASH
MEMORY
MPU
RTC
TIMERS
ICE
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL XIN
XOUT
*IN = Neutral Current
9/17/2010
BATTERY
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
Single Converter Technology is a registered trademark of Maxim Integrated
Products, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Phase Compensation (±7°)
Three Battery-Backup Modes:
Brownout Mode
LCD Mode
Sleep Mode
Wake-Up on Pin Events and Wake-on-Timer
1µA in Sleep Mode
Flash Security
In-System Program Update
8-Bit MPU (80515), Up to 5MIPS
Full-Speed MPU Clock in Brownout Mode
LCD Driver:
6 Common Segment Drivers
Up to 56 Selectable Pins
Up to 51 Multifunction DIO Pins
Hardware Watchdog Timer (WDT)
I2C/MICROWIRE™ EEPROM Interface
SPI Interface with Flash Program Capability
Two UARTs for IR and AMR
IR LED Driver with Modulation
Industrial Temperature Range
100-Pin Lead-Free LQFP Package
v1.2 © 2008–2011 Teridian Semiconductor Corporation 1

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71M6543G pdf, ピン配列
71M6543F/H and 71M6543G/GH Data Sheet
3.1 Theory of Operation .............................................................................................................. 75
3.2 Battery Modes....................................................................................................................... 75
3.2.1 BRN Mode ................................................................................................................ 78
3.2.2 LCD Mode................................................................................................................. 78
3.2.3 SLP Mode ................................................................................................................. 79
3.3 Fault and Reset Behavior...................................................................................................... 80
3.3.1 Events at Power-Down .............................................................................................. 80
3.3.2 IC Behavior at Low Battery Voltage ........................................................................... 81
3.3.3 Reset Sequence........................................................................................................ 81
3.3.4 Watchdog Timer (WDT) Reset................................................................................... 81
3.4 Wake-Up Behavior................................................................................................................ 82
3.4.1 Wake on Hardware Events ........................................................................................ 82
3.4.2 Wake on Timer.......................................................................................................... 84
3.5 Data Flow and MPU/CE Communication ............................................................................... 84
4 Application Information............................................................................................................... 86
4.1 Connecting 5 V Devices........................................................................................................ 86
4.2 Directly Connected Sensors .................................................................................................. 86
4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts ............................................. 87
4.4 System Using Current Transformers ..................................................................................... 88
4.5 Metrology Temperature Compensation.................................................................................. 89
4.5.1 Distinction Between Standard and High-Precision Parts ............................................ 89
4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G ..................................... 90
4.5.3 Temperature Coefficients for the 71M6543H and 71M6543GH .................................. 90
4.5.4 Temperature Coefficients for the 71M6xx3................................................................. 90
4.5.5 Temperature Compensation for VREF and Shunt Sensors ........................................ 90
4.5.6 Temperature Compensation of VREF and Current Transformers ............................... 92
4.6 Connecting I2C EEPROMs .................................................................................................... 94
4.7 Connecting Three-Wire EEPROMs ....................................................................................... 94
4.8 UART0 (TX/RX) .................................................................................................................... 94
4.9 Optical Interface (UART1) ..................................................................................................... 94
4.10 Connecting the Reset Pin...................................................................................................... 95
4.11 Connecting the Emulator Port Pins........................................................................................ 96
4.12 Flash Programming............................................................................................................... 96
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4.12.1 Flash Programming via the ICE Port.......................................................................... 96
4.12.2 Flash Programming via the SPI Port.......................................................................... 96
4.13 MPU Demonstration Code..................................................................................................... 96
4.14 Crystal Oscillator................................................................................................................... 97
4.15 Meter Calibration................................................................................................................... 97
5 Firmware Interface....................................................................................................................... 98
5.1 I/O RAM Map –Functional Order ........................................................................................... 98
5.2 I/O RAM Map – Alphabetical Order ..................................................................................... 104
5.3 Reading the Info Page (71M6543H and 71M6543GH only).................................................. 118
5.4 CE Interface Description ..................................................................................................... 120
5.4.1 CE Program ............................................................................................................ 120
5.4.2 CE Data Format ...................................................................................................... 120
5.4.3 Constants................................................................................................................ 120
5.4.4 Environment............................................................................................................ 121
5.4.5 CE Calculations....................................................................................................... 121
5.4.6 CE Front-End Data (Raw Data) ............................................................................... 122
5.4.7 CE Status and Control............................................................................................. 123
v1.2
© 2008–2011 Teridian Semiconductor Corporation
3


3Pages


71M6543G 電子部品, 半導体
71M6543F/H and 71M6543G/GH Data Sheet
Tables
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15
Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16
Table 3: Multiplexer and ADC Configuration Bits.................................................................................... 19
Table 4. RCMD[4:0] Bits ........................................................................................................................ 23
Table 5: Remote Interface Read Commands ......................................................................................... 23
Table 6: I/O RAM Control Bits for Isolated Sensor.................................................................................. 24
Table 7: Inputs Selected in Multiplexer Cycles ....................................................................................... 26
Table 8: CKMPU Clock Frequencies...................................................................................................... 30
Table 9: Memory Map............................................................................................................................ 31
Table 10: Internal Data Memory Map ..................................................................................................... 32
Table 11: Special Function Register Map............................................................................................... 32
Table 12: Generic 80515 SFRs - Location and Reset Values ................................................................. 33
Table 13: PSW Bit Functions (SFR 0xD0) ............................................................................................... 34
Table 14: Port Registers (SEGDIO0-15) ................................................................................................ 35
Table 15: Stretch Memory Cycle Width .................................................................................................. 35
Table 16. 80515 PCON SFR Register (SFR 0x87).................................................................................... 36
Table 17: Baud Rate Generation............................................................................................................ 36
Table 18: UART Modes ......................................................................................................................... 37
Table 19: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 37
Table 20: The S1CON (UART1) Register (SFR 0x9B)............................................................................. 38
Table 21: PCON Register Bit Description (SFR 0x87).............................................................................. 38
Table 22: Timers/Counters Mode Description ........................................................................................ 39
Table 23: Allowed Timer/Counter Mode Combinations........................................................................... 39
Table 24: TMOD Register Bit Description (SFR 0x89) ............................................................................ 39
Table 25: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 40
Table 26: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 41
Table 27: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41
Table 28: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 41
Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 41
Table 30: The T2CON Bit Functions (SFR 0xC8) .................................................................................... 42
Table 31: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42
Table 32: External MPU Interrupts ......................................................................................................... 42
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Table 33: Interrupt Enable and Flag Bits ................................................................................................ 43
Table 34: Interrupt Priority Level Groups................................................................................................ 43
Table 35: Interrupt Priority Levels .......................................................................................................... 44
Table 36: Interrupt Priority Registers (IP0 and IP1)................................................................................. 44
Table 37: Interrupt Polling Sequence ..................................................................................................... 45
Table 38: Interrupt Vectors .................................................................................................................... 45
Table 39: Flash Memory Access ............................................................................................................ 47
Table 40: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH ............................... 48
Table 41: Flash Security ........................................................................................................................ 49
Table 42: Clock System Summary ......................................................................................................... 51
Table 43: RTC Control Registers ........................................................................................................... 52
Table 44: I/O RAM Registers for RTC Temperature Compensation........................................................ 53
Table 45: NV RAM Table Structure............................................................Error! Bookmark not defined.
Table 46: I/O RAM Registers for RTC Interrupts .................................................................................... 55
Table 47: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56
Table 48: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59
6
© 2008–2011 Teridian Semiconductor Corporation
v1.2

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部品番号部品説明メーカ
71M6543F

Energy Meter ICs

Teridian Semiconductor
Teridian Semiconductor
71M6543G

Energy Meter ICs

Teridian Semiconductor
Teridian Semiconductor
71M6543GH

Energy Meter ICs

Teridian Semiconductor
Teridian Semiconductor
71M6543H

Energy Meter ICs

Teridian Semiconductor
Teridian Semiconductor


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