DataSheet.jp

KSZ8841-16MVL の電気的特性と機能

KSZ8841-16MVLのメーカーはMicrel Semiconductorです、この部品の機能は「Single-Port Ethernet MAC Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 KSZ8841-16MVL
部品説明 Single-Port Ethernet MAC Controller
メーカ Micrel Semiconductor
ロゴ Micrel Semiconductor ロゴ 




このページの下部にプレビューとKSZ8841-16MVLダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

KSZ8841-16MVL Datasheet, KSZ8841-16MVL PDF,ピン配置, 機能
KSZ8841-16/32MQL/MVL/MVLI/MBL
Single-Port Ethernet MAC Controller
with Non-PCI Interface
Rev. 1.6
General Description
The KSZ8841-series single-port chip includes PCI and
non-PCI CPU interfaces, and are available in 8/16-bit and
32-bit bus designs. This datasheet describes the
KSZ8841M-series of non-PCI CPU interface chips. For
information on the KSZ8841 PCI CPU interface chips,
refer to the KSZ8841P datasheet.
The KSZ8841M is a single chip, mixed analog/digital
device offering Wake-on-LAN technology for effectively
addressing Fast Ethernet applications. It consists of a Fast
Ethernet MAC controller, an 8-bit, 16-bit, and 32-bit
generic host processor interface and incorporates a unique
dynamic memory pointer with 4-byte buffer boundary and
a fully utilizable 8KB for both TX and RX directions in host
buffer interface.
The KSZ8841M is designed to be fully compliant with the
appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8841M, the
KSZ8841MVLI, also can be ordered (see “Ordering
Information section).
LinkMD®
Physical signal transmission and reception are enhanced
through the use of analog circuitry, making the design
more efficient and allowing for lower-power consumption.
The KSZ8841M is designed using a low-power CMOS
process that features a single 3.3V power supply with 5V
tolerant I/O. It has an extensive feature set that offers
management information base (MIB) counters and CPU
control/data interfaces.
The KSZ8841M includes a unique cable diagnostics
feature called LinkMD®. This feature determines the length
of the cabling plant and also ascertains if there is an open
or short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8841M
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Functional Diagram
P 1 H P A u to
M D I/M D I-X
1 0 /1 0 0
B a s e -T /T X
PHY
H ost M AC
E m b e d d e d P ro ce sso r
In te rfa c e
8 ,1 6 , o r 3 2 -b it G e n e ric
H o s t In te rfa c e
N o n -P C I
CPU
B us
In te rfa c e
U n it
QMU
DMA
C hannel
P 1 L E D [3 :0 ]
www.DataSheet4U.com E E P R O M I / F
LE D
D riv e r
RXQ
4KB
TXQ
4KB
C o n tro l
R e g is te rs
M IB
C o u n te rs
EEPR O M
In te rfa c e
Figure 1. KSZ8841M Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
Product names used in this datasheet are for identification purposes
only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2007
M9999-102207-1.6

1 Page





KSZ8841-16MVL pdf, ピン配列
Micrel, Inc.
Ordering Information
Part Number
KSZ8841-16MQL
KSZ8841-32MQL
KSZ8841-16MVL
KSZ8841-32MVL
KSZ8841-16MVLI
KSZ8841-32MVLI
KSZ8841-16MBL
KSZ8841-16MBLI
KSZ8841-16MQL-Eval
KSZ8841-16MBL-Eval
KSZ8841-16/32 MQL/MVL/MBL
Temperature Range
0oC to 70oC
0oC to 70oC
0oC to 70oC
0oC to 70oC
–40oC to +85oC
–40oC to +85oC
0oC to 70oC
–40oC to +85oC
Package
128-Pin PQFP
128-Pin PQFP
128-Pin LQFP
128-Pin LQFP
128-Pin LQFP
128-Pin LQFP
100-Ball LFBGA
100-Ball LFBGA
Evaluation Board for the KSZ8841-16MQL
Evaluation Board for the KSZ8841-16MBL
Revision History
Revision
1.0
1.1
Date
06/30/05
08/08/05
1.2 10/04/05
1.3 11/01/05
1.4 03/31/06
1.5 4/10/07
1.6 10/22/07
Summary of Changes
First released Preliminary Information.
Updated General Description, Functional Diagram, Pin Description and Features.
Added this Revision History Table and Loopback support sections.
Update Power Saving bit description in P1PHYCTRL and P1SCSLMD registers.
Updated Figure 12/13/14 Asynchronous Timing and Table 16/17/18 parameters, PQFP
package information.
Added QMU RX Flow Control High Watermark QRFCR register and updated body text
Improve the ARDY low time in read cycle to 40 ns and in write cycle to 50 ns during QMU
data register access
Add KSZ8841-16MBL 100-Ball BGA package information
www.DataSheet4U.com
October 2007
3 M9999-102207-1.6


3Pages


KSZ8841-16MVL 電子部品, 半導体
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Bank 16 RXQ Memory Information Register (0x0A): RXMIR....................................................................................... 65
Bank 17 TXQ Command Register (0x00): TXQCR ...................................................................................................... 65
Bank 17 RXQ Command Register (0x02): RXQCR ..................................................................................................... 65
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR ........................................................................................ 66
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR ....................................................................................... 66
Bank 17 QMU Data Register Low (0x08): QDRL ......................................................................................................... 67
Bank 17 QMU Data Register High (0x0A): QDRH ....................................................................................................... 67
Bank 18 Interrupt Enable Register (0x00): IER ............................................................................................................ 68
Bank 18 Interrupt Status Register (0x02): ISR ............................................................................................................. 69
Bank 18 Receive Status Register (0x04): RXSR ......................................................................................................... 70
Bank 18 Receive Byte Count Register (0x06): RXBC.................................................................................................. 70
Bank 18 Early Transmit Register (0x08): ETXR........................................................................................................... 71
Bank 18 Early Receive Register (0x0A): ERXR ........................................................................................................... 71
Bank 19 Multicast Table Register 0 (0x00): MTR0....................................................................................................... 71
Bank 19 Multicast Table Register 1 (0x02): MTR1....................................................................................................... 72
Bank 19 Multicast Table Register 2 (0x04): MTR2....................................................................................................... 72
Bank 19 Multicast Table Register 3 (0x06): MTR3....................................................................................................... 72
Bank 19 Power Management Control and Status Register (0x08): PMCS .................................................................. 72
Banks 20 – 31: Reserved ............................................................................................................................................. 73
Bank 32 Chip ID and Enable Register (0x00): CIDER ................................................................................................. 73
Bank 32 Chip Global Control Register (0x0A): CGCR ................................................................................................. 74
Banks 33 – 41: Reserved ............................................................................................................................................. 74
Bank 42 Indirect Access Control Register (0x00): IACR .............................................................................................. 75
Bank 42 Indirect Access Data Register 1 (0x02): IADR1 ............................................................................................. 75
Bank 42 Indirect Access Data Register 2 (0x04): IADR2 ............................................................................................. 75
Bank 42 Indirect Access Data Register 3 (0x06): IADR3 ............................................................................................. 75
Bank 42 Indirect Access Data Register 4 (0x08): IADR4 ............................................................................................. 75
Bank 42 Indirect Access Data Register 5 (0x0A): IADR5 ............................................................................................ 75
Bank 43– 44: Reserved ................................................................................................................................................ 75
Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR ....................................................................... 76
Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR......................................................................... 77
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR............................................................................................... 77
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR ............................................................................................. 78
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR............................................................... 78
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR ..................................................... 78
Bank 46: Reserved ....................................................................................................................................................... 79
Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT ................................................................................................ 79
Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL ........................................................................ 80
Bank 48: Reserved ....................................................................................................................................................... 80
Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD ................................................................. 81
Bank 49 Port 1 Control Register 4 (0x02): P1CR4....................................................................................................... 82
Bank 49 Port 1 Status Register (0x04): P1SR ............................................................................................................. 83
Banks 50 – 63: Reserved ............................................................................................................................................. 84
MIB (Management Information Base) Counters............................................................................................................... 85
Additional MIB Information ........................................................................................................................................... 86
Absolute Maximum Ratings(1) ............................................................................................................................................ 87
wwOwpe.DraatainSgheReta4Utin.cgoms(1) ............................................................................................................................................................ 87
Electrical Characteristics(1) ................................................................................................................................................ 88
Timing Specifications ......................................................................................................................................................... 89
Asynchronous Timing without using Address Strobe (ADSN = 0) ............................................................................... 89
Asynchronous Timing using Address Strobe (ADSN) .................................................................................................. 90
Asynchronous Timing using DATACSN ....................................................................................................................... 91
October 2007
6 M9999-102207-1.6

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ KSZ8841-16MVL データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
KSZ8841-16MVIL

Single-Port Ethernet MAC Controller

Micrel Semiconductor
Micrel Semiconductor
KSZ8841-16MVL

Single-Port Ethernet MAC Controller

Micrel Semiconductor
Micrel Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap