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AZC199-02S データシート PDF ( 特性, スペック, ピン接続図 )

部品番号 AZC199-02S
部品説明 Low Capacitance ESD Protection Array
メーカ Amazing Microelectronic
ロゴ Amazing Microelectronic ロゴ 
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AZC199-02S Datasheet, AZC199-02S PDF,ピン配置, 機能
AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
Features
z ESD Protect for 2 high-speed I/O lines
z Provide ESD protection for each line to
IEC 61000-4-2,(ESD) (contact/air) ±16kV
IEC 61000-4-4 (EFT) Level-3, 55A (5/50ns)
IEC 61000-4-5 (Lightning) 5A (8/20μs)
z For low operating voltage applications: 5V,
4.2V, 3.3V, 2.5V etc.
z Low capacitance : 1.6pF typical
z Fast turn-on and Low clamping voltage
z Array of ESD rated diodes with internal
equivalent TVS diode
z Solid-state silicon-avalanche and active circuit
triggering technology
z Green part
Applications
z Video Graphics Cards
z Digital Visual Interface (DVI)
z USB2.0 Power and Data lines protection
z Notebook and PC Computers
z Monitors and Flat Panel Displays
Circuit Diagram
12
Description
AZC199-02S is a design which includes ESD
rated diode arrays to protect high speed data
interfaces. The AZC199-02S has been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD).
AZC199-02S is a unique design which includes
ESD rated, low capacitance steering diodes and
a unique design of clamping cell which is an
equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
the transient to ground line. The internal unique
design of clamping cell prevents over-voltage on
the data line, protecting any downstream
components.
AZC199-02S may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
Pin Configuration
GND
3
3
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12
I/O I/O
JEDEC SOT23-3L (Top View)
Revision 2009/03/12 ©2009 Amazing Micro.
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AZC199-02S pdf, ピン配列
AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
Typical Characteristics
2.4 Typical Variation of CIN vs. VIN
2.1
1.8
1.5
1.2
0.9
0.6
f = 1MHz, T=25 oC,
0.3
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Input Voltage (V)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.0
Typical Variation of CIO-to-IO vs. VIN
f = 1MHz, T=25 oC,
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Input Voltage (V)
5.0
12
11
10
9
8
7
6
5
4
3
2
1
0
4.5
Clamping Voltage vs. Peak Pulse Current
Waveform
Parameters:
tr=8μs
td=20μs
5.0 5.5 6.0 6.5
Peak pulse Current (A)
7.0
Forward Clamping Voltage vs. Peak Pulse Current
5
4
3
2
Waveform
1
Parameters:
tr=8μs
td=20μs
0
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
Peak pulse Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
8
6
V_pulse
Pulse from a
transmission line
100ns
TLP_I
+
TLP_V DUT
-
4
I/O to GND
2
0
0 2 4 6 8 10 12
Transmission Line Pulsing (TLP) Voltage (V)
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Revision 2009/03/12 ©2009 Amazing Micro.
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AZC199-02S 電子部品, 半導体
Mechanical Details
AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
SOT23-3L PACKAGE DIAGRAMS
TOP VIEW
SIDE VIEW
END VIEW
PACKAGE DIMENSIONS
www.DataSheet4U.com
Revision 2009/03/12 ©2009 Amazing Micro.
6
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