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PDF CY7C1916KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1916KV18 | |
| Descripción | 18-Mbit DDR II SRAM Two-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
18-Mbit DDR II SRAM
Two-Word Burst Architecture
18-Mbit DDR II SRAM Two-Word Burst Architecture
Features
Configurations
■ 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)
■ 333-MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD)
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Selection Guide
CY7C1316KV18 – 2 M × 8
CY7C1916KV18 – 2 M × 9
CY7C1318KV18 – 1 M × 18
CY7C1320KV18 – 512 K × 36
Functional Description
The CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and
CY7C1320KV18 are 1.8 V synchronous pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1316KV18
and two 9-bit words in the case of CY7C1916KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘0’ internally in the case of CY7C1316KV18 and
CY7C1916KV18. On CY7C1318KV18 and CY7C1320KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1318KV18 and two 36-bit words in the case of
CY7C1320KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Description
Maximum operating frequency
Maximum operating current
www.DataSheet4U.com
×8
×9
× 18
× 36
333 MHz
333
440
440
450
560
300 MHz
300
420
420
430
520
250 MHz
250
370
370
380
460
200 MHz
200
330
330
340
400
167 MHz
167
300
300
310
360
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58905 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 28, 2011
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CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
Pin Configuration
The pin configurations for CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 follow.[1]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C1316KV18 (2 M × 8)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
R/W
NWS1
K NC/144M LD
A NC/36M
B
NC NC NC
A NC/288M K
NWS0
A
NC NC
C NC NC NC VSS A A A VSS NC NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC VDDQ VDD
VSS
VDD
VDDQ
NC
DQ1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
DQ6
NC VDDQ VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC NC NC VSS A A A VSS NC NC
P NC NC DQ7 A A C A A NC NC
R
TDO
TCK
A
A
A
C
A
A
A TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
1
A CQ
B NC
C NC
D NC
E NC
F NC
G NC
H DOFF
J NC
K NC
L NC
M NC
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P NC
R TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
CY7C1916KV18 (2 M × 9)
4567
R/W NC
K NC/144M
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC/288M
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
AACA
8
LD
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-58905 Rev. *C
Page 5 of 32
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CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
Truth Table
The truth table for the CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 follow.[2, 3, 4, 5, 6, 7]
Operation
Write cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No operation
Standby: Clock stopped
K
L–H
L–H
L–H
Stopped
LD
L
L
H
X
R/W DQ
DQ
L D(A1) at K(t + 1) D(A2) at K(t + 1)
H Q(A1) at C(t + 1) Q(A2) at C(t + 2)
X High Z
X Previous State
High Z
Previous State
Burst Address Table
(CY7C1318KV18, CY7C1320KV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
Write Cycle Descriptions
The write cycle description table for CY7C1316KV18 and CY7C1318KV18 follows.[2, 8]
BWS0/ BWS1/ K
NWS0 NWS1
K
Comments
L L L–H – During the data portion of a write sequence
CY7C1316KV18 both nibbles (D[7:0]) are written into the device.
CY7C1318KV18 both bytes (D[17:0]) are written into the device.
L L – L–H During the data portion of a write sequence
CY7C1316KV18 both nibbles (D[7:0]) are written into the device.
CY7C1318KV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence
CY7C1316KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1318KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C1316KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1318KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C1316KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1318KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C1316KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1318KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
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2. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1318KV18 and CY7C1320KV18, ‘A1’ represents address location latched by the devices when transaction was initiated and ‘A2’ represents the addresses
sequence in the burst. On CY7C1316KV18 and CY7C1916KV18, ‘A1’ represents A + ‘0’ and ‘A2’ represents A + ‘1’.
5. ‘t’ represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the ‘t’ clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-58905 Rev. *C
Page 11 of 32
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| PDF Descargar | [ Datasheet CY7C1916KV18.PDF ] | |
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