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PDF CY7C1165KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1165KV18 | |
| Descripción | 18-Mbit QDR II SRAM Four-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1161KV18, CY7C1176KV18
CY7C1163KV18, CY7C1165KV18
18-Mbit QDR® II+ SRAM Four-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 550-MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
With Read Cycle Latency of 2.5 cycles:
CY7C1161KV18 – 2 M x 8
CY7C1176KV18 – 2 M x 9
CY7C1163KV18 – 1 M x 18
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
CY7C1165KV18 – 512 K x 36
Functional Description
The CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and
CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to ‘turnaround’ the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1161KV18), 9-bit words (CY7C1176KV18), 18-bit
words (CY7C1163KV18), or 36-bit words (CY7C1165KV18) that
burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
Maximum operating frequency
Maximum operating current
www.DataSheet4U.com
550 MHz
550
x8 760
x9 760
500 MHz
500
710
710
450 MHz
450
650
650
400 MHz
400
600
600
Unit
MHz
mA
x18 780
x36 1100
720
1020
670
930
610
850
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58911 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 24, 2011
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CY7C1161KV18, CY7C1176KV18
CY7C1163KV18, CY7C1165KV18
Pin Configuration
The pin configurations for CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and CY7C1165KV18 follow.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1161KV18 (2 M x 8)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
WPS
NWS1
K NC/144M RPS
A NC/36M
B
NC NC NC
A NC/288M K
NWS0
A
NC NC
C NC NC NC VSS A NC A VSS NC NC
D NC D4 NC VSS VSS VSS VSS VSS NC NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC D7 NC VSS A A A VSS NC NC
P NC NC Q7 A
A QVLD A
A NC NC
R
TDO
TCK
A
A
A NC A
A
A TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
1
A CQ
B NC
C NC
D NC
E NC
F NC
G NC
H DOFF
J NC
K NC
L NC
M NC
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P NC
R TDO
2
NC/72M
NC
NC
D5
NC
NC
D6
VREF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
CY7C1176KV18 (2 M x 9)
4567
WPS
NC
K NC/144M
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC/288M
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
QVLD
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A A NC A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
2. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-58911 Rev. *C
Page 5 of 29
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CY7C1161KV18, CY7C1176KV18
CY7C1163KV18, CY7C1165KV18
Truth Table
The truth table for CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and CY7C1165KV18 follows. [3, 4, 5, 6, 7, 8]
Operation
K RPS WPS
DQ
DQ
DQ
DQ
Write cycle:
L-H H [9] L [10] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read cycle:
L-H L [10] X Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and
half cycles; read data on
two consecutive K and K
rising edges.
NOP: No operation
L-H H H D = X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
Standby: Clock stopped Stopped X X Previous state Previous state
Previous state
Previous state
Write Cycle Descriptions
The write cycle description table for CY7C1161KV18 and CY7C1163KV18 follows. [3, 11]
BWS0/ BWS1/
NWS0 NWS1
K
K
Comments
L L L–H – During the data portion of a write sequence
CY7C1161KV18 both nibbles (D[7:0]) are written into the device.
CY7C1163KV18 both bytes (D[17:0]) are written into the device.
L L – L-H During the data portion of a write sequence
CY7C1161KV18 both nibbles (D[7:0]) are written into the device.
CY7C1163KV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence
CY7C1161KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1163KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C1161KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1163KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C1161KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1163KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C1161KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1163KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
www3.DXat=a‘SDhone'et Ct4aUre.’,cHom= Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tristate condition.
5. ‘A’ represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. ‘t’ represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ‘t’ clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
11.
Is based
portions
on a write cycle that was initiated in accordance with Write Cycle Descriptions
of a write cycle, as long as the setup and hold requirements are achieved.
table.
NWS0,
NWS1,
BWS0,
BWS1,
BWS2,
and
BWS3
can
be
altered
on
different
Document Number: 001-58911 Rev. *C
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| PDF Descargar | [ Datasheet CY7C1165KV18.PDF ] | |
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