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PDF ISL6113 Data sheet ( Hoja de datos )
| Número de pieza | ISL6113 | |
| Descripción | (ISL6113 / ISL6114) Dual Slot PCI-E Hot Plug Controllers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6113, ISL6114
September 25, 2007
FN6457.0
Dual Slot PCI-E Hot Plug Controllers
The ISL6113, ISL6114 both target the PCI-Express Add-in card
hot swap application. Together with a pair of N-Channel and
P-Channel MOSFETs, and two sense resistors per slot, either
provides compliant hot plug power control to any combination
of two PCI-Express X1, X4, X8 or X16 slots.
The ISL6113, ISL6114 feature a programmable current
regulated (CR) maximum level for a programmable period to
each voltage load so that both fault isolation protection and
imperviousness to electrical transients are provided.
For each +12V supply, the CR level is set by a resistor value
depending on the needs of the PCI-Express connector (X1, X4,
X8 or X16) to be powered. This resistor is a sub-ohm standard
value current sense resistor one for each slot and the voltage
across this resistor is compared to a 50mV reference providing
a nominal CR protection level adequately above the specific
slot maximum limits. The 3.3V supply uses a 15mΩ sense
resistor compared to a 50mV reference to provide 3.3A of
maximum regulated current to all connector sizes. The
3.3VAUX is internally monitored and controlled to provide a
nominal maximum of 1A of AUX output current.
The CR period for each slot is set by a separate external
capacitor on the associated CFILTER pin. Once the CR period
has expired, the IC then quickly turns off its associated FETs
thus unloading the faulted card from the supply voltage rails. A
nominal 3.3V must always be present on the AUXI pin for
proper IC bias; this should be the 3.3VAUX supply if used, if not
the AUXI pin is tied directly to the 3VMAIN supply. Both ICs
employ a card presence detection input that disables the MAIN
and AUX enabling inputs if it is not pulled low. Output voltage
monitoring with both PCI-E Reset Not and Power Good Not
reporting along with OC Fault reporting are provided. Whereas
the ISL6113 has the same GATE drive and response
characteristics as the ISL6112, the ISL6114 has a lower turn-on
GATE drive current allowing for the use of smaller
compensation capacitors and thus much faster response to
Way Overcurrent (WOC) conditions. Additionally, the ISL6114
does not turn-on with the CR feature invoked as do the
ISL6112, ISL6113 allowing for shorter CR programmed
periods.The ISL6113, ISL6114 are footprint compatible for all
common pins, but not entirely function compatible with the
ISL6112’s QFN package as there are I/O differences.
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Features
• Dual PCI-E Slot Hot Swap Power Control and Distribution
• Highest Accuracy External RSENSE Current Monitoring
On Main Supplies
• Programmable Current Regulation Protection Function for
X1, X4, X8, X16 Connectors
• Programmable Current Regulation Duration
• Programmable In-rush Protection During Turn-On
• Latch-off or Retry Modes After Failure
• Pb-free (RoHS Compliant)
Applications
• PCI-Express Servers
• Power Supply Distribution and Control
• Hot Swap/Electronic Breaker Circuits
• Network Hubs, Routers, Switches
• Hot Swap Bays, Cards and Modules
IF 3.3VAUX NOT
IMPLEMENTED
12VINA 12VSENSEA 12VOUTA 3VINA 3VSENSEA 3VOUTA
VSTBYA
PRSNTB
PRSNTA
FORONA
12VGATEA
3VGATEA
VAUXA
FAULTA
PWRGDA
FORONB
AUXENA
ONA
ISL6113, ISL6114
PERSTA
GPO_A0
GPO_B0
AUXENB
ONB
GPI_A0
GPI_BO
CFILTERA
PERSTB
PWRGDB
FAULTB
VAUXB
CFILTERB
GND
VSTBYB
12VGATEB
3VGATEB
12VINB 12VSENSEB 12VOUTB 3VINB 3SENSEB 3VOUTB
IF 3.3VAUX NOT
IMPLEMENTED
FIGURE 1. TYPICAL ISL6113, ISL6114 BLOCK DIAGRAM
APPLICATION IMPLEMENTATION
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6113, ISL6114
Pin Descriptions (Continued)
PIN NAME
FUNCTION
3, 34
12VGATEA,
12VGATEB
12VMAIN gate drive output, connects to gate of an external P-Channel MOSFET. During power-up, this pin is
pulled down with a 25µA (5µA for ISL6114) current to control the dv/dt ramp of the output voltage to the slot. During
CR, the voltage on this pin is modulated to maintain a constant current into the load. During power-down or
latch-off for an overcurrent fault, this pin is pulled high to 12VIN by internal sources.
14,
3VGATEA,
3VMAIN gate drive outputs connects to gate of an external N-Channel MOSFET. During power-up this pin charges
23
3VGATEB
up with a 25µA (5µA for ISL6114) current to control the dv/dt ramp of the output voltage to the slot load. During
CRTIM the voltage on this pin is modulated to maintain a constant current into the load. During power-down or
latch-off for an overcurrent fault this pin is pulled low by internal sources.
37, 18
PERSTA,
PERSTB
100ms delayed report of MAIN supplies output voltage compliance.
2, 35
CFILTERA,
CFILTERB
A capacitor connected between each of these pins and ground sets the current regulated duration (tFILTER) for
each slot. tFILTER is the amount of time for which a slot remains in current limit before its circuit breaker is tripped.
17, 33,
46
GND
IC ground reference
7,19, 20, NC No Connect
30
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5
FN6457.0
September 25, 2007
5 Page 
ISL6113, ISL6114
the ISL6113, ISL6114 respectively, CLOAD is the load
capacitance, and CGATE is the total GATE capacitance
including CISS of the external MOSFET and any external
capacitance connected from the GATE output pin to the
GATE reference, GND or source.
An estimate for the output slew rate of 3.3V outputs and 12V
outputs where there is little or no external 12VGATE output
capacitors, can be taken from Equation 2:
V O U T dv/dt
=
-----I--L---I--M-------
CLOAD
(EQ. 2)
where ILIM = 50mV/RSENSE and CLOAD is the load
capacitance. Note: As a consequence, the CR duration,
tFILTER must be programmed to exceed the time it takes to
fully charge the output load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate
Control)
The 3.3V outputs act as source followers. In this mode of
operation, VSOURCE = [VGATE – VTH(ON)] until the
associated output reaches 3.3V. The voltage on the gate of
the MOSFET will then continue to rise until it reaches 12V,
which ensures minimum rDS(ON). For the 12V outputs, when
the MOSFET is optionally configured as a Miller integrator to
adjust the VOUT ramp time by having a CGD, which is
connected between the MOSFET’s gate and drain. In this
configuration, the feedback action from drain to gate of the
MOSFET causes the voltage at the drain of the MOSFET to
slew in a linear fashion at a rate estimated by Equation 3:
ISL6113 VOUTdv/dt
=
-2---5----μ----A--
CGD
ISL6114 VOUTdv/dt
=
-5----μ----A---
CGD
(EQ. 3)
Tables 1 and 2 approximate the output slew-rate for various
values of CGATE when start-up is dominated by GATE
capacitance (external CGATE from GATE pin to ground plus
CGS of the external MOSFET for the 3.3V rail; CGD for the
12V rail).
TABLE 1. ISL6113 3.3V AND 12V OUTPUT SLEW-RATE
SELECTION FOR GATE CAPACITANCE
DOMINATED START-UP
| IGATE | = 25µA
CGATE or CGD
0.01µF*
dv/dt (LOAD)
2.5V/ms
0.022µF*
1.136V/ms
www.DataSh0e.e0t447Uµ.Fcom
0.1µF
0.532 V/ms
0.250V/ms
*Values in this range will be affected by the internal parasitic
capacitances of the MOSFETs used and should be verified
empirically.
TABLE 2. ISL6114 3.3V AND 12V OUTPUT SLEW-RATE
SELECTION FOR GATE CAPACITANCE
DOMINATED START-UP
| IGATE | = 5µA
CGATE or CGD
0.01µF*
dv/dt (LOAD)
0.5V/ms
0.022µF*
0.23V/ms
0.047µF
0.106 V/ms
0.1µF
0.050V/ms
*Values in this range will be affected by the internal parasitic
capacitances of the MOSFETs used and should be verified
empirically.
During turn-on, the ISL6113 invokes the current regulation
(CR) feature to limit inrush current whereas the ISL6114
disables the CR feature during turn-on thus allowing a
shorter programmed tFILTER. Both ICs monitor for a severe
or Way Overcurrent (WOC) condition such as a short at this
time.
Note that all of these performance estimates and guidelines
are useful only for first order time and loading expectations,
as they do not look at other significant loading factors.
Figures 3 through 11 realistically illustrate the discussed
turn-on performance topic with the noted loading and
compensation conditions. Notice the degree of control over
the in-rush current and the GATE ramp rate as the CGD and
CGS values are changed providing for highly customized
turn on characteristics.
In some scope shots although the CFILTER shows a ramping
in the absence of excessive displayed loading current the
CFILTER is responding to the other MAIN supply current that
is not displayed.
All scope shots were taken from the ISL6113EVAL1Z or
ISL6114EVAL1Z platform with any component changes are
noted.
12VOUT
12VGATE
12 IOUT
CFILTER
CGD = 6.8nF
CGS = 22nF
FIGURE 3. ISL6113 12VMAIN START-UP RLOAD = 10Ω,
CLOAD = 470µF
11 FN6457.0
September 25, 2007
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ISL6113.PDF ] | |
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