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PDF CY8C24633 Data sheet ( Hoja de datos )
| Número de pieza | CY8C24633 | |
| Descripción | PSoC Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C24633
PSoC® Programmable System-on-Chip
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8 × 8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC® Blocks)
❐ Four Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ High speed 8-bit SAR ADC optimized for motor control
■ Precision, Programmable Clocking
❐ Internal ±5% 24/48 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to eight Analog Inputs on GPIO plus two additional analog
inputs with restricted routing
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
❐ I2C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free development Software (PSoC Designer™)
❐ Full-Featured In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
www.DataSheet4U.com
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-20160 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 20, 2010
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CY8C24633
The Analog System
The Analog system is composed of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block is comprised of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific appli-
cation requirements. Some of the more common PSoC analog
functions (most available as user modules) are listed below.
■ Filters (2 and 4 pole band pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a Core
Resource)
■ 1.3V reference (as a System Resource)
■ DTMF dialer
■ Modulators
■ Correlators
■ Peak detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
Figure 2. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASD11
ASC21
ACI2[3:0]
8-Bit SAR ADC
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
P0[7:0]
Interface to
Digital System
Ref Hi
Ref Lo
AGND
Analog Reference
Re fe r e nce
Ge ne r ator s
AGNDIn
Ref In
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
www.DataSheet4U.com
Document Number: 001-20160 Rev. *D
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CY8C24633
Register Reference
This section lists the registers of the CY8C24633 PSoC device by using mapping tables, in offset order.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Convention
R
W
L
C
#
Description
Read register or bit(s)
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
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Document Number: 001-20160 Rev. *D
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