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CY14B256Q1 の電気的特性と機能

CY14B256Q1のメーカーはCypress Semiconductorです、この部品の機能は「256-Kbit (32 K X 8) Serial (SPI) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14B256Q1
部品説明 256-Kbit (32 K X 8) Serial (SPI) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14B256Q1 Datasheet, CY14B256Q1 PDF,ピン配置, 機能
CY14B256Q1
CY14B256Q2
CY14B256Q3
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14B256Q1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
High-speed serial peripheral interface (SPI)
40-MHz clock rate
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4,1/2, or entire array
Low power consumption
Single 3 V +20%, –10% operation
Average active current of 10 mA at 40-MHz operation
Logic Block Diagram
Industry standard configurations
Industrial temperature
CY14B256Q1 has identical pin configuration to industry
standard 8-pin NV memory
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B256Q1/CY14B256Q2/CY14B256Q3
combines a 256-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 32 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B256Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B256Q1
No
Yes
CY14B256Q2
Yes
Yes
No No
CY14B256Q3
Yes
Yes
Yes
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
32 K X 8
SRAM Array
32 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
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SI
Instruction
register
Address
Decoder
A0-A14
D0-D7
Data I/O register
SO
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53882 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 24, 2011
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CY14B256Q1 pdf, ピン配列
CY14B256Q1
CY14B256Q2
CY14B256Q3
Device Operation
CY14B256Q1/CY14B256Q2/CY14B256Q3 is a 256-Kbit
nvSRAM memory with a nonvolatile element in each memory
cell. All the reads and writes to nvSRAM happen to the SRAM
which gives nvSRAM the unique capability to handle infinite
writes to the memory. The data in SRAM is secured by a STORE
sequence that transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (VCAP) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
The 256-Kbit memory array is organized as 32 K words × 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the chip select (CS) pin and
accessed through serial input (SI), serial output (SO), and serial
clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (one quarter,
one half, or full array) using BP0 and BP1 pins in the Status
Register. Further, the HOLD pin is used to suspend any serial
communication without resetting the serial sequence.
CY14B256Q1/CY14B256Q2/CY14B256Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their
application. The feature summary is given in Table 1.
Table 1. Feature Summary
Feature
WP
VCAP
HSB
AutoStore
Power-Up
RECALL
Hardware
STORE
Software
STORE
Software
RECALL
CY14B256Q1 CY14B256Q2 CY14B256Q3
Yes No Yes
No Yes Yes
No No Yes
No Yes Yes
Yes Yes Yes
No No Yes
Yes Yes Yes
Yes Yes Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables user to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the Memory Access
section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and two bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
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Document Number: 001-53882 Rev. *E
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CY14B256Q1 電子部品, 半導体
CY14B256Q1
CY14B256Q2
CY14B256Q3
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14B256Q1/CY14B256Q2/CY14B256Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of the first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.
Data Transmission - SI and SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14B256Q1/CY14B256Q2/CY14B256Q3 has two separate
pins for SI and SO, which can be connected with the master as
shown in Figure 2 on page 6.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
most significant bit (MSB). This is valid for both address and data
transmission.
The 256-Kbit serial nvSRAM requires a 2-byte address for any
read or write operation. However, since the address is only
15-bits, it implies that the first MSB that is fed in is ignored by the
device. Although this bit is ‘don’t care’, Cypress recommends
that this bit is treated as 0 to enable seamless transition to higher
memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14B256Q1/CY14B256Q2/CY14B256Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. Refer to Table 2 on page 8 for details.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
Status Register
CY14B256Q1/CY14B256Q2/CY14B256Q3 has an 8-bit Status
Register. The bits in the Status Register are used to configure
the SPI bus. These bits are described in the Table 4 on page 9.
Figure 2. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
CS1
HOLD1
CS2
HOLD2
SCK SI
SO
CY14B256Qx
CS HOLD
SCK SI
SO
CY14B256Qx
CS HOLD
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Document Number: 001-53882 Rev. *E
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共有リンク

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部品番号部品説明メーカ
CY14B256Q

256-Kbit (32 K x 8) SPI nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B256Q1

256-Kbit (32 K X 8) Serial (SPI) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B256Q2

256-Kbit (32 K X 8) Serial (SPI) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B256Q3

256-Kbit (32 K X 8) Serial (SPI) nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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