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CY14B101PA の電気的特性と機能

CY14B101PAのメーカーはCypress Semiconductorです、この部品の機能は「1-Mbit (128 K X 8) Serial (SPI) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14B101PA
部品説明 1-Mbit (128 K X 8) Serial (SPI) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14B101PA Datasheet, CY14B101PA PDF,ピン配置, 機能
PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
1-Mbit (128 K × 8) Serial (SPI) nvSRAM
with Real Time Clock
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
Internally organized as 128 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power Up RECALL)
or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real time clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 uA (typical)
40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and read (with special fast read
instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 250 uA
Sleep mode current of 8 uA
Industry standard configurations
Operating voltages:
• CY14C101PA : VCC = 2.4 V to 2.6 V
• CY14B101PA : VCC = 2.7 V to 3.6 V
• CY14E101PA : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14X101PA combines a 1 Mbit nvSRAM[1] with a
full-featured RTC in a monolithic integrated circuit with serial SPI
interface. The memory is organized as 128 K words of 8 bits
each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
You can also initiate the STORE and RECALL operations
through SPI instruction.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacture ID/
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory Data
&
Address Control
Quantrum Trap
128 K x 8
SRAM
128 K x 8
STORE
RECALL
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RDRTC/WRTC
WRSR/RDSR/WREN
Status Register
Xin
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-54392 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 21, 2011
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CY14B101PA pdf, ピン配列
PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Pinouts
Figure 1. Pin Diagram - 16-Pin SOIC
NC
VRTCbat
Xout
Xin
1
2
3
4
WP
HOLD
VRTCcap
VSS
5
6
7
8
16 VCC
15 INT/SQW
Top View
not to scale
14
13
12
VCAP
SO
SI
11 SCK
10 CS
9 HSB
Table 1. Pin Definitions
Pin Name
CS
I/O Type
Input
SCK
Input
SI
SO
WP
HOLD
HSB
Input
Output
Input
Input
Input/Output
VCAP
Power Supply
VRTCcap
VRTCbat
Xout
Xin
INT/SQW
Power Supply
Power Supply
Output
Input
Output
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NC No Connect
VSS Power Supply
VCC Power Supply
Description
Chip Select: Activates the device when pulled LOW. Driving this pin HIGH puts the device in low
power standby mode.
Serial clock: Runs at speeds up to a maximum of fSCK. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
Serial input: Pin for input of all SPI instructions and data
Serial output: Pin for output of data through SPI
Write Protect: Implements hardware write protection in SPI
HOLD pin: Suspends Serial Operation
Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then
a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
Capacitor backup for RTC: Left unconnected if VRTCbat is used
Battery backup for RTC: Left unconnected if VRTCcap is used
Crystal output connection
Crystal input connection
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the
watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or
LOW (open drain). In calibration mode, a 512 Hz square wave is driven out. In the square wave
mode, you may select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as a
continuous output.
No connect. This pin is not connected to the die.
Ground
Power supply
Document #: 001-54392 Rev. *C
Page 3 of 44
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CY14B101PA 電子部品, 半導体
PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X101PA provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X101PA can run at speeds up to
104 MHz except RDRTC and READ instruction.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. CY14X101PA supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X101PA operates as a slave device and may share the SPI
bus with multiple CY14X101PA devices or other SPI devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW.
The CY14X101PA is selected when the CS pin is LOW. When
the device is not selected, data through the SI pin is ignored and
the serial output pin (SO) remains in a high-impedance state.
wwwN.oDteatAaSnhewet4inUs.tcroumction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14X101PA allows SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X101PA has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
CY14X101PA requires a 3-byte address for any read or write
operation. However, because the address is only 17 bits, it
implies that the first seven bits that are fed in are ignored by the
device. Although these seven bits are ‘don’t care’, Cypress
recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X101PA uses the standard opcodes for memory accesses.
In addition to the memory accesses, CY14X101PA provides
additional opcodes for the nvSRAM specific functions: STORE,
RECALL, AutoStore Enable, and AutoStore Disable. Refer to
Table 2 on page 9 for details on opcodes.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS and the SO pin remains tri-stated.
Status Register
CY14X101PA has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 4 on page 10.
Document #: 001-54392 Rev. *C
Page 6 of 44
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部品番号部品説明メーカ
CY14B101PA

1-Mbit (128 K X 8) Serial (SPI) nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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