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PDF ISLA216P Data sheet ( Hoja de datos )

Número de pieza ISLA216P
Descripción 16-Bit 250MSPS/200MSPS/130MSPS ADC
Fabricantes Intersil 
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No Preview Available ! ISLA216P Hoja de datos, Descripción, Manual

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16-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA216P
The ISLA216P is a family of low power, high performance
16-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA216P is part of a pin-compatible portfolio
of 12 to 16-bit A/Ds with maximum sample rates ranging from
130MSPS to 500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA216P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
• SNR @ 250/200/130MSPS
• 75.0/76.6/77.5dBFS fIN = 30MHz
• 72.1/72.6/72.4dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
• 87/91/96dBc fIN = 30MHz
• 81/80/82dBc fIN = 363MHz
• Total Power Consumption = 786mW @ 250MSPS
Features
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
• SPI Programmable Fine Gain and Offset Control
• Support for Multiple ADC Synchronization
• Optimized Output Timing
• Nap and Sleep Modes
• 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKP
CLKN
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
VINP
VINN
VCM
SHA
16-BIT
250 MSPS
ADC
+
SPI
CONTROL
DIGITAL
ERROR
CORRECTION
D[14:0]P
D[14:0]N
Pin-Compatible Family
MODEL
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
January 13, 2011
FN7574.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/

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ISLA216P pdf
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ISLA216P
Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)
PIN NUMBER
4
8, 9
10, 11
15
16
18
22, 23
24, 25
31
36
40
44
46
48
52
56
60
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
VCM
VINN
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D14
D12
D10
D8
RLVDS
CLKOUT
D6
D4
D2
D0
SDO
CSB
SCLK
SDIO
AVSS
CMOS PIN FUNCTION
Common Mode Output
Analog Input Negative
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
DDR Logical Bits 14, 15
DDR Logical Bits 12, 13
DDR Logical Bits 10, 11
DDR Logical Bits 8, 9
LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)
CMOS Clock Output
DDR Logical Bits 6, 7
DDR Logical Bits 4, 5
DDR Logical Bits 2, 3
DDR Logical Bits 0, 1
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA216P13IRZ
ISLA216P13 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
ISLA216P20IRZ
ISLA216P20 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
ISLA216P25IRZ
ISLA216P25 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
Coming Soon
ISLA216P13IR1Z
ISLA216P13 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
Coming Soon
ISLA216P20IR1Z
ISLA216P20 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
Coming Soon
ISLA216P25IR1Z
ISLA216P25 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
ISLA216P25EVAL
Evaluation Board
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216P. For more information on MSL please see techbrief TB363.
5 FN7574.0
January 13, 2011
Datasheet pdf - http://www.DataSheet4U.net/

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ISLA216P arduino
www.DataSheet.co.kr
Timing Diagrams
ISLA216P
INP
INN
CLKN
CLKP
tA
tCPD
CLKOUT
D[14/12/…/2/0]
LATENCY = L CYCLES
tDC
tPD
ODD
N-L
EVEN ODD EVEN
N-L N-L+1 N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 1B. CMOS
FIGURE 1. TIMING DIAGRAMS
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN MAX
(Note 5) TYP (Note 5)
ADC OUTPUT
Aperture Delay
tA
114
RMS Aperture Jitter
jA
75
Input Clock to Output Clock Propagation
Delay
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3 2.75
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
Input Clock to Data Propagation Delay
tPD
1.65
2.4
3.5
Output Clock to Data Propagation Delay,
LVDS Mode
tDC Rising/Falling Edge
-0.1 0.16 0.5
Output Clock to Data Propagation Delay,
CMOS Mode
tDC Rising/Falling Edge
-0.1 0.2 0.65
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
0.4 0.06
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
0.02
0.35
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
DLL recovery time after
Synchronous Reset
52
Latency (Pipeline Delay)
L
10
UNITS
ps
fs
ns
ns
ps
ns
ns
ns
ns
ns
µs
cycles
11
FN7574.0
January 13, 2011
Datasheet pdf - http://www.DataSheet4U.net/

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