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PDF ISL76322 Data sheet ( Hoja de datos )
| Número de pieza | ISL76322 | |
| Descripción | 16-Bit Long-Reach Video Automotive Grade SERDES | |
| Fabricantes | Intersil | |
| Logotipo |  |
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16-Bit Long-Reach Video Automotive Grade SERDES
ISL76322
The ISL76322 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel video
at the remote end by the deserializer. The fully featured register
set is programmed through the industry standard I2C.
Related Literature
• See FN6827, ISL34341 Data Sheet “WSVGA 24-Bit
Long-Reach Video SERDES with Bi-directional Side-Channel”
Features
• 16-bit RGB Transport Over a Single Differential Pair
• 6MHz to 50MHz Pixel Clock Rates
• AECQ100 Qualified Component
• Bi-directional Auxiliary Data Transport without Extra Bandwidth
and Over the Same Differential Pair
• Hot-plugging with Automatic Resynchronization Every HSYNC
• Selectable Clock Edge for Parallel Data Output
• DC-balanced with Industry Standard 8b/10b Line Code Allows
AC-coupling, Providing Immunity Against Ground Shifts
• 16 Programmable Settings Each for Transmitter Amplitude
Boost and Pre-emphasis and Receiver Equalization, Allow for
Longer Cable Lengths and Higher Data Rates
• Slew Rate Control and Spread Spectrum Capability on Outputs
Reduce the Potential for EMI
• Same Device for Serializer and Deserializer Simplifies Inventory
Applications
• Video Entertainment Systems
• Remote Cameras
3.3V
1.8V VDD_IO
3.3V
1.8V VDD_IO
16
VIDEO
SOURCE
RGB
VSYNC
HSYNC
DE
PCLK_IN
ISL76322
SERIALIZER
27nF
SERIOP
27nF
SERION
27nF
SERIOP
RGB
27nF
ISL76322
SERION DESERIALIZER
VSYNC
HSYNC
DE
REF_CLK
PCLK_IN
PCLK_OUT
16
VIDEO
TARGET
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VDD_IO
FIGURE 1. TYPICAL APPLICATION
January 31, 2011
FN7611.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL76322
Ordering Information
PART NUMBER
(Notes 3, 4, 5)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL76322ARZ
ISL76322 ARZ
-40 to +105
48 Ld QFN
L48.7x7C
NOTES:
3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL76322. For more information on MSL please see techbrief TB363.
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5
January 31, 2011
FN7611.0
5 Page 
ISL76322
suitable (perhaps niobium oxide), but “classic” electrolytic
capacitors frequently have ESR values of above 1Ω, that nullify
any decoupling effect above the 1kHz to 10kHz frequency range.
Capacitors of 0.1µF offer low impedance in the 10MHz to 20MHz
region, and 1000pF capacitors in the 100MHz to 200MHz region.
In general, one of the lower value capacitors should be used at
each supply pin on the IC. Figure 5 shows the grounding of the
various capacitors to the pin corresponding to the supply pin.
Although all the ground supplies are tied together, the PCB layout
should be arranged to emulate this arrangement (at least for the
smaller value (high frequency) capacitors), as much as possible.
120Ω
120Ω
120Ω
120Ω
120Ω
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
I2C Interface
The I2C interface allows access to internal registers used to
configure the SERDES and to obtain status information. A
serializer must be assigned a different address than its
deserializer counterpart if the side channel is used. The upper 5
bits are permanently set to 011 11 and the lower 2 bits
determined by pins as follows:
0 1 1 1 1 I2CA1 I2CA0 R/W
Thus, 4 SERDES can reside on the same bus. By convention,
when all address pins are tied low, the device address is referred
to as 0x78.
SCL and SDA are open drain to allow multiple devices to share
the bus. If not used, SCL and SDA should be tied to VDD_IO.
Exposed Pad
While it is not a required electrical connection, it is
recommended that the exposed pad on the bottom of the
package be soldered to the circuit board. This will ensure that the
full power dissipation of the package can be utilized. The pad
should be connected to ground and not left floating. For best
thermal conductivity, 16 vias should connect the footprint for the
exposed pad on the circuit board to the ground plane. This
connection is not required for basic operation of the chip.
COPPER PAD
120Ω
10µF
0.1µF
FIGURE 5. POWER SUPPLY BYPASSING
VIAS
16x
FIGURE 6. LAYOUT FOR THE EXPOSED PAD
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January 31, 2011
FN7611.0
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL76322.PDF ] | |
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