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PDF AS9C25256M2036L Data sheet ( Hoja de datos )
| Número de pieza | AS9C25256M2036L | |
| Descripción | (AS9C25256M2036L / AS9C25128M2036L) 2.5V 256/128K X 36 Synchronous Dual-port SRAM | |
| Fabricantes | Alliance Semiconductor Corporation | |
| Logotipo |  |
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September 2004
Preliminary Information
AS9C25256M2036L
AS9C25128M2036L
®
www.DataSheet4U.com
2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
• True Dual-Port memory cells that allow simulta-
neous access of the same memory location
• Organisation: 262,144/131,072 x 36[1]
• Fully Synchronous, independent operation on
both ports
• Selectable Pipeline or Flow-Through output
mode
• Fast clock speeds in Pipeline output mode: 250
MHz operation (18Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline out-
put mode
• Asynchronous output enable control
• Fast OE access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
• 18/17[1]-bit counter with Increment, Hold and
Repeat features on each port
• Dual Chip enables on both ports for easy depth
expansion
Note:
1. AS9C25256M2036L/AS9C25128M2036L
• Interrupt and Collision Detection Features
• 2.5 V power supply for the core
• LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
• Snooze modes for each port for standby
operation
• 15mA typical standby current in power
down mode
• Available in 256-pin Ball Grid Array
(BGA), 208-pin Plastic Quad Flatpack
(PQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
• Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature
-250 -200 -166 -133 Units
Minimum cycle time
4 5 6 7.5 ns
Maximum Pipeline clock frequency
250 200 166 133 MHz
Maximum Pipeline clock access time 2.8 3.4 3.6 4.2 ns
Maximum flow-through clock frequency
150
133
100
83 MHz
Maximum flow-through clock access time
6.5
7.5
10
12
ns
Maximum operating current
TBD
350
300
260
mA
Maximum snooze mode current
18 18 18 18 mA
9/30/04; v.1.3
Alliance Semiconductor
P. 1 of 30
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
Ball Assignment - 208-ball fpBGA
®
AS9C25256M2036L
AS9C25128M2036L
www.DataSheet4U.com
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A DQ19A DQ18A VSS TDO COLA A16A A12A A8A BE1A VDD CLKA INCA A4A A0A OPTA DQ17A VSS A
B DQ20B VSS DQ18B TDI A17[1]A A13A A9A BE2A CE0A VSS ADSA A5A A1A
NC VDDQB DQ16A DQ15B B
C VDDQA DQ19B VDDQB PL/FTA INTA A14A A10A BE3A CE1A VSS R/WA A6A A2A VDD DQ16B DQ15A VSS C
D DQ22A VSS DQ21A DQ20A A15A A11A A7A BE0A VDD OEA RPTA A3A VDD DQ17B VDDQA DQ14A DQ14B D
E DQ23A DQ22B VDDQB DQ21B
DQ12A DQ13B VSS DQ13A E
F VDDQA DQ23B DQ24A VSS
VSS DQ12B DQ11A VDDQB F
G DQ26A VSS DQ25A DQ24B
DQ9A VDDQA DQ10A DQ11B G
H VDD DQ26B VDDQB DQ25B
J VDDQA VDD VSS ZZB
K DQ28B VSS DQ27B VSS
AS9C25256M2036L/AS9C25128M2036L
F - 208
Top view
VDD DQ9B VSS DQ10B H
ZZA VDD VSS VDDQB J
DQ7B VDDQA DQ8B VSS K
L DQ29B DQ28A VDDQB DQ27A
DQ6B DQ7A VSS DQ8A L
M VDDQA DQ29A DQ30B VSS
VSS DQ6A DQ5B VDDQB M
N DQ31A VSS DQ31B DQ30A
DQ3B VDDQA DQ4B DQ5A N
P DQ32B DQ32A VDDQB DQ35B TRST A16B A12B A8B BE1B VDD CLKB INCB A4B DQ2A DQ3A VSS DQ4A P
R VSS DQ33A DQ34B TCK A17[1]B A13B A9B BE2B CE0B VSS ADSB A5B A1B NC VDDQA DQ1B VDDQB R
T DQ33B DQ34A VDDQA TMS INTB A14B A10B BE3B CE1B VSS R/WB A6B A2B VSS DQ0B VSS DQ2B T
U VSS DQ35A PL/FTB COLB A15B A11B A7B BE0B VDD OEB RPTB A3B A0B VDD OPTB DQ0A DQ1A U
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Note:
1. Address A17 is a NC for AS9C25128M2036L
9/30/04, v.1.3
Alliance Semiconductor
P. 5 of 30
5 Page 
AS9C25256M2036L
AS9C25128M2036L
®
www.DataSheet4U.com
IDD operating conditions and maximum limits[4] (VDD = 2.5 V ± 100 mV)
Parameter Symbol
Test Conditions
-250 -200 -166 -133 Units
Typ Max Typ Max Typ Max Typ Max
Operating current
(Both ports active)
TBD TBD TBD 350 TBD 300 TBD 260 mA
Pipeline mode --
(PL/FT > VIH)
Operating current
(Both ports active)
Both ports enabled (CEA = CEB = L[3]),
ICC Outputs disabled (IOUT = 0mA), ZZA = ZZB < VIL,
f=fMax[1]
TBD TBD TBD TBD TBD TBD TBD TBD mA
Flow-through mode
(PL/FT < VIL)
Standby current
(Both ports)
Standby current
(One port)
Both ports disabled (CEA = CEB = H),
ISB1 ZZA = ZZB < VIL,
f=fMax[1]
One port enabled (CEA = L and CEB = H)[5],
ISB2 Active port's outputs disabled, ZZA = ZZB < VIL,
f=fMax[1]
TBD TBD TBD 105 TBD 90 TBD 80 mA
TBD TBD TBD 265 TBD 225 TBD 190 mA
Both ports disabled (CEA = CEB = H),
Full standby current
(Both ports)
ISB3
ZZA = ZZB < VIL,
f=0[2]
20 25 20 25 20 25 20 25 mA
Full standby current
(One port)
ISB4
One
CEB
port in Snooze
= L)[5],
(ZZA
>
VIH,
ZZB
<
VIL,
and
Active port's outputs disabled,
TBD TBD TBD 265 TBD 225 TBD 190 mA
f=fMax[1]
Snooze mode
current
IZZ
Both ports in Snooze (ZZA = ZZB > VIH),
f=fMax[1]
15 18 15 18 15 18 15 18 mA
Notes:
1. f=fMax implies address and controls (except OE) are cycling at maximum clock frequency using AC test conditions (Refer AC test conditions).
2. f = 0 implies address and controls are static. Corresponding current numbers indicated are true for both CMOS (VIN > VDDQ - 0.2V or VIN < 0.2V)
and TTL (VIN > VIH or VIN < VIL) level inputs.
3. CEA and CEB are internal signals (CEx = L implies CE0x < VIL and CE1x > VIH, CEx = H implies CE0x > VIH or CE1x < VIL).
4. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
5. “A” and “B” are interchangeable.
9/30/04, v.1.3
Alliance Semiconductor
P. 11 of 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS9C25256M2036L.PDF ] | |
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