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PDF MT9V131 Data sheet ( Hoja de datos )
| Número de pieza | MT9V131 | |
| Descripción | 1/4-Inch SOC VGA CMOS Digital Image Sensor | |
| Fabricantes | Aptina Imaging Corporation | |
| Logotipo |  |
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MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
General Description
General Description
www.DataSheet4U.com
This SOC VGA CMOS image sensor features DigitalClarity⎯Aptina’s breakthrough, low-
noise CMOS imaging technology that achieves CCD image quality (based on signal-to-
noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte-
gration advantages of CMOS.
The MT9V131 is a fully-automatic, single-chip camera, requiring only a power supply,
lens, and clock source for basic operation. Output video is streamed through a parallel 8-
bit DOUT port, as shown in Figure 1. The output pixel clock is used to latch the data,
while FRAME_VALID (FV) and LINE_VALID (LV) signals indicate the active video. The
sensor can be put in an ultra-low power sleep mode by asserting the STANDBY pin.
Output signals can also be tri-stated by de-asserting the OE_BAR pin. The MT9V131
internal registers can be configured using a two-wire serial interface.
The MT9V131 can be programmed to output progressive scan images up to 30 fps in an
8-bit ITU_R BT.656 (YCbCr) formerly CCIR656, YUV, 565RGB, 555RGB, or 444RGB
formats. 10-bit raw Bayer data output can also be selected. The FV and LV signals are
output on dedicated pins, along with a pixel clock (PIXCLK) that is synchronous with
valid data.
Figure 1:
Chip Block Diagram
SCLK
SDATA
SADDR
CLK
STANDBY
OE_BAR
VDD/DGND
VAA/AGND
VAA_PIX
Communication Bus
Sensor Core
. Based on MT9V011
. 668H x 496V (VGA+ Reference)
. 1/4-inch optical format
. Auto black compensation
. Programmable analog gain
. Programmable exposure
. Low power, 10-bit ADCs
Image Flow Processor
. Color correction, gamma,
lens shading correction
. Auto exposure, white balance
. Interpolation and defect
correction
. Flicker avoidance
SRAM Line Buffers
DOUT[7:0]:DOUT_LSB[1:0]
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
The MT9V131 can accept an input clock of up to 27 MHz, delivering 30 fps. With
power-on defaults (see Appendix B on page 28 for recommended defaults), the camera is
configured to deliver 15 fps at 12 MHz and automatically slows down the frame rate in
low-light conditions to achieve longer exposures and better image quality.
Internally, the MT9V131 consists of a sensor core and an image flow processor (IFP). The
sensor core functions to capture raw Bayer-encoded images that are input into the IFP
as shown in Figure 1. The IFP processes the incoming stream to create interpolated,
color-corrected output and controls the sensor core to maintain the desirable exposure
and color balance.
Sensor core and IFP registers are grouped into two separate address spaces, as shown in
Figure 2 on page 6. The internal registers can be accessed through the two-wire serial
interface. Selecting the desired address space can be accomplished by programming
register R0x01, which remains present in both register sets.
PDF: 9989496744/Source: 2860937402
MT9V131_DS - Rev.E 6/10 EN
5 Aptina reserves the right to change products or specifications without notice.
©2006 Aptina Imaging Corporation. All rights reserved.
1 page  
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Ball Assignment
Table 4:
Pin Description for the CLCC Package
www.DataSheet4U.com
Pin Number
20
21
23
31
33
34
35
39
22
13
14
Pin Name
EXTCLK
SCLK
SADDR
ADC_TEST
RESET_BAR
STANDBY
OE_BAR
DNU
SDATA
FLASH
PIXCLK
15
16
45
46
1
2
3
4
8
9
10
11
7, 17, 25, 37, 40, 41,
44, 47
26, 28
32
27, 29
5, 12, 19, 24, 36, 38,
43, 48
6, 18, 30, 42
LINE_VALID
FRAME_VALID
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DOUT_LSB1
DOUT_LSB0
VDD
VAA
VAA_PIX
AGND
DGND
NC
Type
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Supply
Description
Master clock into sensor. Default is 12 MHz (27 MHz maximum).
Serial clock.
Serial interface address select: R0xB8 when HIGH (default).
R0x90 when LOW.
Tie to Vaa_PIX (factory use only).
Asynchronous reset of sensor when LOW. All registers assume factory defaults.
When HIGH, puts the imager in ultra-low power standby mode.
Output_Enable pin. When HIGH, tri-state all outputs except SDATA (tie LOW for
normal operation).
Tie to digital ground.
Serial data I/O.
Flash strobe.
Pixel clock out. Pixel data output are valid during rising edge of this clock. IFP R0x08
[9] inverts polarity.
Frequency = Master clock.
Active HIGH during line of selectable valid pixel data.
Active HIGH during frame of valid pixel data.
ITU_R BT.656/RGB data bit 7 (MSB).
ITU_R BT.656/RGB data bit 6.
ITU_R BT.656/RGB data bit 5.
ITU_R BT.656/RGB data bit 4.
ITU_R BT.656/RGB data bit 3.
ITU_R BT.656/RGB data bit 2.
ITU_R BT.656/RGB data bit 1.
ITU_R BT.656/RGB data bit 0 (LSB).
Raw Bayer 10-bit output.
Raw Bayer 10-bit output (LSB).
Digital power (2.8V).
Supply
Supply
Supply
Supply
Analog power (2.8V).
Pixel array power (2.8V).
Analog ground.
Digital ground.
– No connect.
PDF: 9989496744/Source: 2860937402
MT9V131_DS - Rev.E 6/10 EN
9 Aptina reserves the right to change products or specifications without notice.
©2006 Aptina Imaging Corporation. All rights reserved.
5 Page 
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
Electrical Specifications
www.DataSheet4U.com
The recommended operating temperature ranges from –20°C to +70°C. The sensor
image quality may degrade above +40°C.
Table 8:
DC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Definition
Input high voltage
Input low voltage
Input leakage current
Output high voltage
Output low voltage
Output high current
Output low current
Tri-state output leakage current
Analog operating supply current
Digital operating supply current
Analog standby supply current
Digital standby supply current
Symbol
VIH
VIL
IIN
VOH
VOL
IOH
IOL
IOZ
IAA
IDD
IAA Standby
IDD Standby
Condition
No pull-up resistor; VIN = VDD or
DGND
Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
STDBY = VDD
STDBY = VDD
Min
VDD - 0.25
–0.3
–5.0
Typ
VDD - 0.2
10.0 20.0
10.0 20.0
5.0 8.0
10.0 15.0
0.0 2.5
0.0 2.5
Max
VDD + 0.25
0.8
5.0
Unit
V
V
μA
V
0.2 V
15.0 mA
20.0 mA
5.0 μA
25.0 mA
25.0
20.0 mA
20.0
5.0 μA
5.0 μA
Notes:
1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles before
turning off the master clock. Two master clock cycles are required to place the analog circuitry into
standby, low-power mode.
2. When STANDBY is de-asserted, standby mode is exited immediately (within several master clocks), but
the current frame and the next two frames will be invalid. The fourth frame will contain a valid image.
PDF: 9989496744/Source: 2860937402
MT9V131_DS - Rev.E 6/10 EN
15
Aptina reserves the right to change products or specifications without notice.
©2006 Aptina Imaging Corporation. All rights reserved.
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet MT9V131.PDF ] | |
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