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PDF 64F7055 Data sheet ( Hoja de datos )
| Número de pieza | 64F7055 | |
| Descripción | HD64F7055 | |
| Fabricantes | Renesas Technology | |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
www.DataSheet.in
1 page  
Preface
The SH7055 is a single-chip RISC (reduced instruction set computer) microcomputer that has an
original Hitachi RISC type CPU as its core, and also includes peripheral functions necessary for
system configuration.
The CPU of the SH7055 has a RISC type instruction set, with basic instructions executed in one
system clock cycle, for a higher instruction execution speed. It employs an internal 32-bit
configuration, and offers enhanced data processing performance. The CPU of the SH7055 makes
it possible to create high-performance, high-functionality systems at low cost, even for
applications requiring high speed such as real-time control, which could not be realized with
conventional microcomputers.
The SH7055 is also equipped with on-chip peripheral functions necessary for system
configuration, including a floating-point unit (FPU), large-capacity ROM and RAM, a direct
memory access controller (DMAC), timers, a serial communication interface (SCI), Hitachi
controller area network (HCAN), A/D converter, interrupt controller (INTC), and I/O ports.
In addition, an external memory access support function allows direct connection of ROM and
SRAM, enabling system costs to be greatly reduced.
The SH7055 is an F-ZTAT™ (Flexible Zero Turn-Around Time) version with flash memory as its
on-chip ROM. Flash memory programs can be written with a programmer that supports SH7055
programming, and the flash memory can also be programmed and erased by software. This allows
reprogramming to be carried out by the user with the chip mounted on a board.
This Hardware Manual describes the hardware of the SH7055. Details of instructions can be found
in the Programming Manual.
Related Manual
Covering SH7055 execution instructions:
SH-2E Programming Manual
Please consult your Hitachi sales representative for details of the development environment
system.
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5 Page 
6.5.4 General Illegal Instructions .................................................................................. 88
6.5.5 Floating-Point Instructions ................................................................................... 88
6.6 When Exception Sources Are Not Accepted..................................................................... 89
6.7 Stack Status after Exception Processing Ends................................................................... 90
6.8 Usage Notes ....................................................................................................................... 91
6.8.1 Value of Stack Pointer (SP).................................................................................. 91
6.8.2 Value of Vector Base Register (VBR) ................................................................. 91
6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 91
Section 7 Interrupt Controller (INTC)......................................................................... 93
7.1 Overview............................................................................................................................ 93
7.1.1 Features ................................................................................................................ 93
7.1.2 Block Diagram...................................................................................................... 94
7.1.3 Pin Configuration ................................................................................................. 95
7.1.4 Register Configuration ......................................................................................... 96
7.2 Interrupt Sources................................................................................................................ 97
7.2.1 NMI Interrupts...................................................................................................... 97
7.2.2 User Break Interrupt ............................................................................................. 97
7.2.3 H-UDI Interrupt.................................................................................................... 97
7.2.4 IRQ Interrupts ...................................................................................................... 97
7.2.5 On-Chip Peripheral Module Interrupts ................................................................ 98
7.2.6 Interrupt Exception Vectors and Priority Rankings ............................................. 99
7.3 Description of Registers .................................................................................................... 108
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL) ................................................... 108
7.3.2 Interrupt Control Register (ICR) .......................................................................... 109
7.3.3 IRQ Status Register (ISR) .................................................................................... 110
7.4 Interrupt Operation ............................................................................................................ 112
7.4.1 Interrupt Sequence................................................................................................ 112
7.4.2 Stack after Interrupt Exception Processing .......................................................... 114
7.5 Interrupt Response Time ................................................................................................... 115
7.6 Data Transfer with Interrupt Request Signals ................................................................... 117
7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 117
7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 117
Section 8 User Break Controller (UBC) ..................................................................... 119
8.1 Overview............................................................................................................................ 119
8.1.1 Features ................................................................................................................ 119
8.1.2 Block Diagram...................................................................................................... 120
8.1.3 Register Configuration ......................................................................................... 121
8.2 Register Descriptions......................................................................................................... 121
8.2.1 User Break Address Register (UBAR)................................................................. 121
8.2.2 User Break Address Mask Register (UBAMR) ................................................... 122
8.2.3 User Break Bus Cycle Register (UBBR).............................................................. 124
iii
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