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IS61SPS25632T PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS61SPS25632T
部品説明 256Kx32 Synchronous Pipelined Static RAM
メーカ ISSI
ロゴ ISSI ロゴ 



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IS61SPS25632T Datasheet, IS61SPS25632T PDF,ピン配置, 機能
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
ISSIIS61SPS51218T/D IS61LPS51218T/D
®
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
SINGLE-CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
MAY 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O For SPS
• 2.5V I/O For LPS
• Single cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-150
3.8
6.7
150
-133 Units
4 ns
7.5 ns
133 MHz
DESCRIPTION
The ISSI IS61SPS25632,IS61SPS25636,IS61SPS51218,
IS61LPS25632, IS61LPS25636, and IS61LPS51218 are
high-speed, low-power synchronous static RAMs designed
to provide a burstable, high-performance memory for
communication and networking applications. The
IS61SPS25632 and IS61LPS25632 are organized as
262,144 words by 32 bits and the IS61SPS25636 and
IS61LPS25636 are organized as 262,144 words by 36 bits.
The IS61SPS51218 and IS61LPS51218 are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
1
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