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PDF ADG5408 Data sheet ( Hoja de datos )
| Número de pieza | ADG5408 | |
| Descripción | (ADG5408 / ADG5409) High Voltage Latch-Up Proof | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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DataSheet.in
FEATURES
Latch-up proof
8 kV human body model (HBM) ESD rating
Low on resistance (13.5 Ω)
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADG5408/ADG5409 are monolithic CMOS analog multi-
plexers comprising eight single channels and four differential
channels, respectively. The ADG5408 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2. The ADG5409 switches one of
four differential inputs to a common differential output, as
determined by the 2-bit binary address lines, A0 and A1.
An EN input on both devices enables or disables the device.
When EN is disabled, all channels switch off. The on-resistance
profile is very flat over the full analog input range, which ensures
good linearity and low distortion when switching audio signals.
High switching speed also makes the parts suitable for video
signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
High Voltage Latch-Up Proof,
4-/8-Channel Multiplexers
ADG5408/ADG5409
FUNCTIONAL BLOCK DIAGRAMS
ADG5408
ADG5409
S1 S1A
DA
S4A
D
S1B
DB
S8 S4B
1-OF-8
DECODER
1-OF-4
DECODER
A0 A1 A2 EN
A0 A1 EN
Figure 1.
The ADG5408/ADG5409 do not have VL pins; rather, the logic
power supply is generated internally by an on-chip voltage
generator.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.
2. Low RON.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5408/ADG5409 can be operated
from dual supplies up to ±22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5408/ADG5409 can be operated
from a single rail power supply up to 40 V.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
DataSheet.in
ADG5408/ADG5409
Parameter
Total Harmonic Distortion + Noise
−3 dB Bandwidth
ADG5408
ADG5409
Insertion Loss
CS (Off )
CD (Off )
ADG5408
ADG5409
CD (On), CS (On)
ADG5408
ADG5409
POWER REQUIREMENTS
IDD
ISS
VDD/VSS
25°C −40°C to +85°C −40°C to +125°C Unit
0.012
% typ
50 MHz typ
88 MHz typ
0.8 dB typ
17 pF typ
Test Conditions/Comments
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
VS = 0 V, f = 1 MHz
98
pF typ
VS = 0 V, f = 1 MHz
48
pF typ
VS = 0 V, f = 1 MHz
128
80
50
70
0.001
110
±9/±22
pF typ
pF typ
μA typ
μA max
μA typ
V min/V max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C −40°C to +85°C −40°C to +125°C Unit
0 V to VDD
V
26 Ω typ
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
30 36
0.3
1 1.5
5.5
6.5 8
±0.02
42
1.6
12
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
Drain Off Leakage, ID (Off )
±0.25 ±1
±0.05
±7
nA max
nA typ
±0.4 ±4 ±30 nA max
Channel On Leakage, ID (On), IS (On) ±0.05
nA typ
±0.4 ±4 ±30 nA max
DIGITAL INPUTS
Input High Voltage, VINH
2.0 V min
Input Low Voltage, VINL
0.8 V max
Input Current, IINL or IINH
0.002
μA typ
±0.1 μA max
Digital Input Capacitance, CIN
3
pF typ
Test Conditions/Comments
VS = 0 V to 10 V, IS = −10 mA; see
Figure 26
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 29
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 29
VS = VD = 1 V/10 V; see Figure 25
VIN = VGND or VDD
Rev. 0 | Page 5 of 24
5 Page 
DataSheet.in
A0 1
EN 2
VSS 3
S1A 4
S2A 5
S3A 6
S4A 7
DA 8
16 A1
15 GND
ADG5409
TOP VIEW
(Not to Scale)
14 VDD
13 S1B
12 S2B
11 S3B
10 S4B
9 DB
Figure 4. ADG5409 Pin Configuration (TSSOP)
ADG5408/ADG5409
VSS 1
S1A 2
S2A 3
S3A 4
PIN 1
INDICATOR
ADG5409
TOP VIEW
(Not to Scale)
12 VDD
11 S1B
10 S2B
9 S3B
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.
Figure 5. ADG5409 Pin Configuration (LFCSP)
Table 10. ADG5409 Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
31
VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
42
S1A Source Terminal 1A. This pin can be an input or an output.
53
S2A Source Terminal 2A. This pin can be an input or an output.
64
S3A Source Terminal 3A. This pin can be an input or an output.
75
S4A Source Terminal 4A. This pin can be an input or an output.
86
DA Drain Terminal A. This pin can be an input or an output.
97
DB Drain Terminal B. This pin can be an input or an output.
10 8
S4B Source Terminal 4B. This pin can be an input or an output.
11 9
S3B Source Terminal 3B. This pin can be an input or an output.
12 10
S2B Source Terminal 2B. This pin can be an input or an output.
13 11
S1B Source Terminal 1B. This pin can be an input or an output.
14 12
VDD Most Positive Power Supply Potential.
15 13
GND Ground (0 V) Reference.
16 14 A1 Logic Control Input.
EP Exposed The exposed pad is connected internally. For increased reliability of the solder joints and maximum
Pad thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG5409 Truth Table
A1 A0
XX
00
01
10
11
EN
0
1
1
1
1
On Switch Pair
None
1
2
3
4
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADG5408.PDF ] | |
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