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CL-GD6205 の電気的特性と機能

CL-GD6205のメーカーはCirrus Logicです、この部品の機能は「Single DRAM LCD/VGA Controllers」です。


製品の詳細 ( Datasheet PDF )

部品番号 CL-GD6205
部品説明 Single DRAM LCD/VGA Controllers
メーカ Cirrus Logic
ロゴ Cirrus Logic ロゴ 




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CL-GD6205 Datasheet, CL-GD6205 PDF,ピン配置, 機能
CL-GD62XXwww.DataSheet4U.com
® Preliminary Data Book
FEATURES
s IBM®_VGA hardware-compatible
s Integrated RAMDAC
s Integrated programmable frequency synthesizer
— 65 MHz at 5.0V; 40 MHz at 3.3V
s Supports single 256K x 16 DRAM configuration
— Symmetric or asymmetric RAS/CAS-address DRAM
s Color STN panel support (CL-GD6225/’6235 only)
— Dual-scan color STN panel support (CL-GD6235 only)
— 8- and 16-bit interfaces (no extra components required)
— Up to 256 simultaneous colors from a palette of 256K
s Integrates color TFT panel support
— Supports 9-, 12-, 15-, and 18-bit TFT panels
— Up to 256 simultaneous colors from a palette of 256K
s Connects directly to local bus, ISA bus (PC AT) or PI
bus (CL-GD6205 connects to ISA bus only)
s Windows performance-improvement features
— True packed-pixel addressing
— Improved data latches for block moves
— Color expansion for 8 bits-per-pixel graphics
— 32 x 32 hardware cursor (2 bits-per-pixel)
s Supports 3.3V and 5.0V mixed-voltage operation
s Standby and Suspend modes save power
— Internal timers for backlight control and Standby mode
— Dedicated Hardware-suspend Mode pin
— 32-kHz DRAM refresh clock in Suspend mode
s Frame-Accelerator for low-active power
— No additional DRAMs required
— Supports self-refresh DRAMs
s Simultaneous CRT and LCD (SimulSCAN) operation
(cont.)
Single DRAM LCD/VGA
Controllers for Monochrome/
Color Notebook Computers
OVERVIEW
The CL-GD62XX (CL-GD6205/’6215/’6225/’6235) fam-
ily of advanced single-chip flat panel VGA controllers are
designed for use in portable systems with stringent
power consumption and form-factor requirements.
Product family pin compatibility provides easy upgrade
capability to color or higher-performance systems.
Integration of the frequency synthesizer, RAMDAC,
monochrome and color STN/TFT panel interfaces mini-
mizes the form-factor requirement for color and mono-
chrome graphics subsystems. All necessary panel-
power sequencing logic has been integrated into the
CL-GD62XX family, and a complete graphics subsystem
can be built using only two active components (in less
than three square inches).
The CL-GD62XX family uses a single 256K x 16 DRAM
(or four 256K x 4 DRAMs) for video memory. For added
flexibility, dual-CAS*-DRAM and dual-WE*-DRAM con-
figurations are supported.
With integrated Frame-Accelerator technology, the
CL-GD62XX controllers feature low-power LCD opera-
tion, yet support high LCD panel vertical-refresh rates.
No additional DRAMs are required for frame
(cont.)
Functional
Block Diagram
3.3V
3.3V or 5V
256K x 16
DRAM
3.3V or 5V
CL-GD62XX
160-Pin PQFP
3.3V
or
5V
3.3V
or
5V
5
4
3
2
1
0
ANALOG CRT
5
4
3
2
1
0
REFERENCE FREQUENCY
MONOCHROME OR
COLOR LCD PANEL
October 1993
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CL-GD6205 pdf, ピン配列
CL-GD62XX
LCD VGA Controller Family
www.DataSheet4U.com
Table of Contents — PAGE #s INCORRECT; USE BOOKMARKS
1. PIN INFORMATION ............................... 7
1.1 Pin Diagram for the CL-GD6205.......................... 7
1.2 Pin Diagram for the CL-GD6215.......................... 8
1.3 Pin Diagram for the CL-GD6225 and
CL-GD6235. ......................................................... 9
1.4 Typical Dual Monochrome Panel Connections —
ISA Bus Using 256K x 16 DRAM
with Dual CAS*................................................... 10
1.5 STN Color Panel Connections — ’386SL/’486SL
PI Bus Using 256K x 4 DRAMs ......................... 11
1.6 TFT Color Panel Connections — ’386SX
Local Bus Using 256K x 16 DRAM
with Dual WE* .................................................... 12
1.7 TFT Color Panel Connections — ’386DX
Local Bus Using 256K x 16 DRAMs
with Dual WE* .................................................... 13
1.8 Dual-Scan STN Color Panel — ’486DX Local
Bus/256K x 16 DRAM with Dual CAS*.............. 14
1.9 Pin Summary...................................................... 15
2. DETAILED PIN DESCRIPTIONS ........ 21
2.1 Host Interface — ISA Bus Mode ........................ 21
2.2 Host Interface — ’386SL/’486SL (PI Bus Mode)
(CL-GD6215/’25/’35 only) .................................. 25
2.3 Host Interface — Local Bus
(CL-GD6215/’25/’35 only) .................................. 27
2.4 Dual-Frequency Synthesizer Interface .............. 31
2.5 CRT Interface ..................................................... 32
2.6 Display Memory Interface .................................. 34
2.7 Miscellaneous Pins ............................................ 36
2.8 Power Management Pins................................... 38
2.9 LCD Flat Panel Interface.................................... 40
2.10 Power And Ground Pins .................................... 42
3. FUNCTIONAL DESCRIPTION............ 45
3.1 General............................................................... 45
3.2 Functional Blocks ............................................... 45
3.2.1 CPU Interface ................................................. 45
3.2.2 CPU Write Buffer ............................................ 45
3.2.3 Graphics Controller......................................... 45
3.2.4 Memory Arbitrator ........................................... 45
3.2.5 Memory Sequencer ........................................ 45
3.2.6 CRT Controller ................................................ 45
3.2.7 LCD Flat-Panel Controller .............................. 45
3.2.8 Video FIFO...................................................... 45
3.2.9 Attribute Controller.......................................... 45
3.2.10 Palette DAC .................................................... 46
3.2.11 Dual-Frequency Synthesizer .......................... 46
3.3 Functional Operation.......................................... 46
3.3.1 CPU Access to Registers............................... 46
3.3.2 CPU Access to Display Memory .................... 46
3.3.3 Display Memory Refresh................................ 46
3.3.4 Screen Refresh .............................................. 46
3.4 Performance ...................................................... 46
3.5 Compatibility ...................................................... 46
3.6 Data Bus Interface for 32-Bit Processors.......... 46
3.6.1 486 Burst Mode Support ............................... 47
3.6.2 CL-GD62XX Address Decode and
Latching .......................................................... 47
3.6.3 Bus Cycle Restart .......................................... 47
3.6.4 Other Considerations ..................................... 47
3.7 LCD Flat Panel Interface ................................... 48
3.8 Intelligent Power Management and
Sequencing........................................................ 49
3.8.1 Normal Mode.................................................. 49
3.8.2 Hardware Power-Management Modes.......... 49
3.8.3 Standby Mode ................................................ 49
3.8.3.1 Initiating/Entering Standby Mode................ 50
3.8.3.2 Terminating/Exiting Standby Mode ............. 50
3.8.4 Suspend Mode ............................................... 50
3.8.4.1 Hardware-Suspend Mode........................... 50
3.8.4.2 Software-Suspend Mode ............................ 51
3.8.4.3 Initiating/Entering Suspend Mode............... 51
3.8.4.4 Terminating/Exiting Suspend Mode............ 51
3.8.5 Power Sequencing ......................................... 51
3.8.5.1 LCD Panel Power-Down Sequence ........... 51
3.8.5.2 LCD Panel Power-Up Sequence................ 51
3.8.6 Additional Power Management
Features ......................................................... 52
3.8.6.1 LCD-only Operation
(CRT Disable) ............................................. 52
3.8.6.2 CRT-only Operation
(LCD Panel Disable) ................................... 52
3.8.6.3 Backlight Timer ........................................... 52
3.8.6.4 ACTi Function ............................................. 52
3.9 Internal RAMDAC.......................................... 52
3.9.1 RAMDACVideo Operation.......................... 53
3.9.2 Analog Outputs............................................... 53
3.9.3 Writing to the Color Look-up Table................. 53
3.9.4 Reading from the Color Look-up Table .......... 53
4. CL-GD62XX VIDEO
MODE TABLES ....................................55
4.1 CRT Video Modes ............................................ 55
4.2 LCD Flat Panel Video Modes ........................... 57
October 1993
PRELIMINARY DATA BOOK
TABLE OF CONTENTS
3
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CL-GD6205 電子部品, 半導体
CL-GD62XXwww.DataSheet4U.com
LCD VGA Controller Family
Revision History
Major changes between the previous version, dated September 1992, and this version are listed below.
General
The major addition to this data book is information specific to the CL-GD6235 device.These additions are
labeled as CL-GD6235 only', if they do not apply to other devices in the family. Also, the LCD Timing
(Shadow) registers (Rxx), that were listed with the CR1D[7] register description, have been broken out
into individual register descriptions at the end of Section 6.0.
Specific
Section Revision
1.0 The CL-GD6235 is added to the CL-GD6225 pin diagram. One of the filter capacitors in the AVDD fil-
ter circuit has been changed from '.1't9'1.0' CLF. The Pin Summary Tables for the Host Interfaces
has been consolidated into one table. The Output Loading Parameters have been moved from the
Pin Summary tables to the Electrical Test section.
2.0 The detailed pin descriptions have been modified for consistency and to add the pin numbers to the
individual pins. Information has been added to many of the descriptions.
2.4 The recommended filter circuit components have been changed.
2.5 The IREF circuit for 3.3V operation has been added.
3.0 The functional description has been modified to add CL-GD6235-specific information.
3.8 Standby and Suspend mode descriptions have been modified for clarity. Also, the power sequencing
parameters have been changed.
4.3 The Host Interface Signals table has been included in Section 1.9, Pin Summary.
6.0 The register information has been expanded to include CL-GD6235–specific register data. Register
descriptions have been added for:
CR29 — Configuration register
ROX through REX — LCD Timing registers (these3hadow' registers were described under the
CR1D[7] register description).
7.2 DC Specifications — the CMOS input-threshold and output-limit specifications have been corrected.
An Output Loading table has been added.
7.6 AC Specifications — many of the tables and waveforms have consolidated to reflect operating rela-
tionships, and some new parameters have been added to the Memory Read and Write tables. Most
of the limits are equal to or tighter than the original data. The STN and TFT panel interface timing
specifications have been modified to reflect more current LCD-industry limits.
8.0 Package dimensions have been modified slightly to reflect the latest plastic package.
6 October 1993
PRELIMINARY DATA BOOK

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
CL-GD6205

Single DRAM LCD/VGA Controllers

Cirrus Logic
Cirrus Logic


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