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INS8154 の電気的特性と機能

INS8154のメーカーはNational Semiconductorです、この部品の機能は「N-Channel 128-by-8 Bit RAM Input/Output」です。


製品の詳細 ( Datasheet PDF )

部品番号 INS8154
部品説明 N-Channel 128-by-8 Bit RAM Input/Output
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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INS8154 Datasheet, INS8154 PDF,ピン配置, 機能
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INS&154 N.ChanRel 12&.by.& Bit
RAM Input/Outriit (RAM 1/0)
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m0::r
General Description
Features
~
The RAM Input/Output Chip if'.' LSI device wh/ch
provides random access memor'
Peripheral inter-
facing for microcomputer syste
he RAM portion
contains 1024 bits of static R
anized as 128x8,
The 1/0 portion consists of t
ripheral ports of
eight bits each. Each of the 1/0 im ln the two ports
may be defined as an input or': -output to provide
0 128x8RAM
0 Single +5-volt power s' plV
0 Low power dissipatio
0 Fully static operation
0 Completely TTL com ibl~Î"
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C..D..
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CD
c::r
maximum flexibility. Each port iv be read from or
written to in a parallel (8-bit b ' (mode. To improve
0 Two 8-bit programma ji '1/0 ports
0 1/0 port A has TRI-S ;J'El!!>capability
'<
ëo
efficiency and simplify programrijing in control-based
applications, a single bit of 1/0 II\' either port may be
Set, cleared or read with a single rrilcTOprocessor instruc-
0 Handshake controls
0 Single bit 1/0 operati
strobed mode of operation
with single instruction
t_U0
-
tion. ,ln addition to basic 1/0, one\of the ports, port A,
may be programmed to operate!1 in several types of
strobed mode with handshake. St(obed mode together
with optional interrupt operation permit both high
0 Reduces system packs cou nt
0 Direct interface with JMP
Independent operatio" f RAM and 1/0
::a
»
i:
speed parallel data transfers and:, interface to a wide
variety of peripherals with no external logic.
The RAM 1/0 is an n-channe! silicon gate device
packaged in a 40-pin dual-in-li". package. It operates
~th a single 5.volt power SUI't,Py and is fully TTL
,c<Jmpatible.
,
INS8154 MICROBUSTM Configuration
"
MICROBUS"TM* comfib, le
"'-0CC-C-.-:t-~»g.:J'.a....
s:
:::
CPU'
GRO~
ADDRESS
BUS
DATA
BUS
CONTRDl
BUS
M
1
~C cs'1'
B MEMR
U
INS8154
PORT BUS
PORT. ,BUS
-0
S MEMW
RUET
INRI
NOTE
Th,INTR.g",,1 be.oma_o.ly
""'.o.nb,,dd,
mod, wh,. 0
do" "0
1. th,
0. hu
*Trademark, National Semlconductor Corp,
197BNotlonal Semiconductor
Corp,
DA,B15M4B/Printad
in U.s.A.

1 Page





INS8154 pdf, ピン配列
.,AC Electrical Characteristics (cont'd)
(,," ,
Parameter
WRITE CYCLE
twp NWDS Pulse Width
tAO ACK t ta OBF t (Modes 3 & 4 Only)
tACW ACK Pulse Width (Modes 3 & 4 Only)
tWD Port Data Val id After NWDS t
tpE ACK t ta Valid Output (Mode 4 Only)
tPD ACK t ta Hi-Z (Mode 4 Only)
Output Load Capaeitanee
tWRST Master Reset Pulse Width
Conditions
Min Twypww.DatMaSahxeet4U.cUonmits
300
250
300
300
300
0 125
75
300
ns
ns
ns
ns
ns
ns
pF
ns
Note 1: Ail tlmes measured Irom a valid logie "0" leve! = 0.8 V or a valid logie "1" level = 2.0 V.
Read Cycle
1-""-
m"'.-",~
1
-l',,c l
,"rlOo"""~
I~M'",2
"'""'0"
--y-
1-'" -1 ""1-
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l
'",-'OO.M!I1I
,
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f.-"s-I ",'-
~"IO,";",~
CS" CS,
""
"OS
1=~-1',-t+ii:YiI==X---=1'" 1-
"'1'
BU-S-
-
-
-
-
-
-
-
-
_H-~-
-
-
-
-
-
--1'eo 1- -1"'1-
- - -~~, ---- ,
Write Cycle
I-owcyc
IF"' RAMI-- "-1
1-"'---1
[-'" 1
==>EI=:Ir'",-'OO.M-IIO X-
mm ffi
;"'DA~
1
'--l'osl- --1,,;1-
,ATABOS
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,wos '1--~
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I-,wo~
lWJ;,',"6:~J~,~
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~""""w,,'"
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i-=-r
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--1",1-- -1
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1-
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3Pages


INS8154 電子部品, 半導体
www.DataSheet4U.com
Operation
NRST NRDS NWDS eso
RAM OPERATIONS
Data Bus -->RAM
RAM -->Data Bus
110 0
1
10 10
BIT OPERATIONS
Set Bit Port A
Clear Bit Port A
Read Bit Port A
Set Bit Port B
Clear Bit Port B
Read Bit Port B
. PORT OPERATIONS
PortA--> Data Bus
Data Bus -->Port A
Port B -->Data Bus
Data Bus -->Port B
110 0
110 0
10
10
110 0
110 0
10
10
10
10
110 0
10
10
110 0
CONTROL OPERATIONS
Data Bus -+ Output Definition A
110 0
Data Bus -+ Output Definition B
1 1 0 el
Data Bus -+ Mode Definition Register 1 1 r:J 0
D!SABLE FUNCTION
Master Reset
Data Bus -+ Hi-Z
Data Bus -+ Hi-Z
Data Bus -+ Hi-Z
0 XXX
1110
1XX
1
1XXX
eS1 MIlO AG A5 A4 A3 A2 A1 AO
1 1 XXXXXXX
11
1 1 XXXXXXX
1 11
1 0 0 0 1 0 B2 B1 BO
1 0 0 0 0 0 B2 B1 BO
1 0 0 0 X 0 B2 B1 BO
1 0 0 0 1 1 B2 B1 BO
1 0 0 0 0 1 B2 B1 BO
1 0 0 0 X 1 B2 B1 BO
1 0 0 10 0 0 0 0
1 0 0 10 0 0 0 0
1 0 0 10 0 0 0 1
1 0 0 10 0 0 0 1
1 0 0 10 0 0 10
1 0 0 10 0 0 1 1
1 0 Ir 1 0 0 1 0 0
X X XXXXXXX
1 X X X X X X Ir x
X X XXXXXXX
0 X XXXXXXX
Figure 1. Tmth Table
G

6 Page



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共有リンク

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部品番号部品説明メーカ
INS8154

N-Channel 128-by-8 Bit RAM Input/Output

National Semiconductor
National Semiconductor


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