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H57V2622GMR の電気的特性と機能

H57V2622GMRのメーカーはHynix Semiconductorです、この部品の機能は「256Mb Dual Die Synchronous DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 H57V2622GMR
部品説明 256Mb Dual Die Synchronous DRAM
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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H57V2622GMR Datasheet, H57V2622GMR PDF,ピン配置, 機能
256Mb : x32 Dual Die Synchronous DRAM
www.DataSheet4U.com
256M (8Mx32bit) Hynix SDRAM
Memory
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Oct. 2009
1

1 Page





H57V2622GMR pdf, ピン配列
111www.DataSheet4U.com
Synchronous DRAM Memory 256Mbit
H57V2622GMR Series
DESCRIPTION
The Hynix H57V2622GMR Synchronous DRAM (Dual Die) ideally suited for the consumer memory applications which
requires large memory density and high bandwidth uses Hinix’s 128Mb SDR monolithic die and has similar functional-
ity.
Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous
DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization
with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32
Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.
The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,
8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is
initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the
column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,
randon-access operation.
Read and write accesses to the Hynix Synchronous DRAM are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted
and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).
All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).
Rev 1.0 / Oct. 2009
3


3Pages


H57V2622GMR 電子部品, 半導体
111www.DataSheet4U.com
Synchronous DRAM Memory 256Mbit
H57V2622GMR Series
BALL DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Clock :
CLK INPUT The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
Clock Enable:
CKE INPUT Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
CS
INPUT
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
INPUT
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
INPUT
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
RAS, CAS, WE
INPUT
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0 ~ DQM3
I/O
Data Mask:
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
I/O
Data Input / Output:
Multiplexed data input / output pin
VDD / VSS SUPPLY Power supply
VDDQ / VSSQ SUPPLY I/O Power supply
NC - No connection : These pads should be left unconnected
Rev 1.0 / Oct. 2009
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
H57V2622GMR

256Mb Dual Die Synchronous DRAM

Hynix Semiconductor
Hynix Semiconductor
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256Mb Dual Die Synchronous DRAM

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H57V2622GMR-60X

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H57V2622GMR-75X

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