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H57V2562GFR の電気的特性と機能

H57V2562GFRのメーカーはHynix Semiconductorです、この部品の機能は「256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O」です。


製品の詳細 ( Datasheet PDF )

部品番号 H57V2562GFR
部品説明 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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H57V2562GFR Datasheet, H57V2562GFR PDF,ピン配置, 機能
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
www.DataSheet4U.com
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Aug. 2009
1

1 Page





H57V2562GFR pdf, ピン配列
111www.DataSheet4U.com
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
DESCRIPTION
The Hynix H57V2562GFR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the con-
sumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of
4,194,304 x 16 I/O.
Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous
DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization
with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16
Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.
The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,
8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is
initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the
column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,
randon-access operation.
Read and write accesses to the Hynix Synchronous DRAM are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).
Rev 1.0 / Aug. 2009
3


3Pages


H57V2562GFR 電子部品, 半導体
111www.DataSheet4U.com
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
54_TSOPII Pin DESCRIPTIONS
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A12
RAS, CAS, WE
LDQM, UDQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock :
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
Clock Enable:
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:
Controls output buffers in read mode and masks input data in write mode
Data Input / Output:
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection : These pads should be left unconnected
Rev 1.0 / Aug. 2009
6

6 Page



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部品番号部品説明メーカ
H57V2562GFR

256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

Hynix Semiconductor
Hynix Semiconductor


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