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PDF IXDF502 Data sheet ( Hoja de datos )
| Número de pieza | IXDF502 | |
| Descripción | (IXDx502) 2 Ampere Dual Low-Side Ultrafast MOSFET Drivers | |
| Fabricantes | IXYS | |
| Logotipo |  |
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IXDF502 / IXDI502 / IXDN502
2 Ampere Dual Low-Side Ultrafast MOSFET Drivers
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 2 Amps
• High 2A Peak Output Current
• Wide Operating Range: 4.5V to 30V
• -55°C to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 1000pF in <10ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in Single Chip
Applications
• Driving MOSFETs and IGBTs
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Class D Switching Amplifiers
• Power Charge Pumps
General Description
The IXDF502, IXDI502 and IXDN502 each consist of two 2-
Amp CMOS high speed MOSFET Gate Drivers for driving
the latest IXYS MOSFETs & IGBTs. Each of the Dual
Outputs can source and sink 2 Amps of Peak Current while
producing voltage rise and fall times of less than 15ns. The
input of each Driver is TTL or CMOS compatible and is
virtually immune to latch up. Patented* design innovations
eliminate cross conduction and current "shoot-through".
Improved speed and drive capabilities are further enhanced
by very quick & matched rise and fall times.
The IXDF502 is configured with one Gate Driver Inverting
plus one Gate Driver Non-Inverting. The IXDI502 is config-
ured as a Dual Inverting Gate Driver, and the IXDN502 is
configured as a Dual Non-Inverting Gate Driver.
The IXDF502, IXDI502 and IXDN502 are each available in
the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-
age, and the 6-Lead DFN (D1) package, (which occupies
less than 65% of the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Part Number Description
IXDF502PI
IXDF502SIA
IXDF502SIAT/R
IXDF502D1
IXDF502D1T/R
IXDI502PI
IXDI502SIA
IXDI502SIAT/R
IXDI502D1
IXDI502D1T/R
IXDN502PI
IXDN502SIA
IXDN502SIAT/R
IXDN502D1
IXDN502D1T/R
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Dual, with one
Driver Inverting
and one Driver
Non-Inverting
Dual, with both
Drivers
Inverting
Dual, with both
Drivers Non-
Inverting
NOTE: All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
First Release
DS99573B(03/10)
1 page  
IXDF502 / IXDI502 / IXDN502www.DataSheet4U.com
Pin Description
PIN PACKAGE
2 SOIC, DIP
1 DFN
3 SOIC, DIP
2 DFN
4 SOIC, DIP
3 DFN
5 SOIC, DIP
4 DFN
6 SOIC, DIP
5 DFN
7 SOIC, DIP
6 DFN
SYMBOL
IN A
GND
IN B
OUT B
VCC
OUT A
FUNCTION
DESCRIPTION
A Channel Input
Ground
B Channel Input
A Channel Input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry,
this pin provides ground reference for the entire chip. This pin
should be connected to a low noise analog ground plane for
optimum performance.
B Channel Input signal-TTL or CMOS compatible.
B Channel Output
Supply Voltage
A Channel Output
B Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
Positive power-supply voltage input. This pin provides power
to the entire chip. The range for this voltage is from 4.5V to
30V.
A Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configuration
IXDF502
IXDI502
IXDN502
1 NC
NC 8
2 IN A OUT A 7
3 GND
4 INB
V6
S
OUT B 5
1 NC
NC 8
2 IN A OUT A 7
3 GND
4 INB
V6
S
OUT B 5
1 NC
NC 8
2 IN A OUT A 7
3 GND
4 INB
V6
S
OUT B 5
8 Lead PDIP (PI)
8 Pin SOIC ((SSII)A)
IXDF402
8 Lead PDIP (PI)
8 Pin SOIC ((SSII)A)
IXDI402
8 Lead PDIP (PI)
8 Pin SOIC (S(SI)IA)
IXDN402
6 Lead DFN (D1)
(Bottom View)
6 OUTA IN A 1
5 Vc c GND 2
4 OUTB IN B 3
6 Lead DFN (D1)
(Bottom View)
6 OUTA IN A 1
5 Vc c GND 2
4 OUTB IN B 3
6 Lead DFN (D1)
(Bottom View)
6 OUTA IN A 1
5 Vc c GND 2
4 OUTB IN B 3
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 4 - Characteristics Test Diagram
Vcc
10uF
0.01uF
1 NC
2 In A
3 Gnd
4 In B
NC 8
Out A 7
Vcc 6
Out B 5
Agilent 1147A
Current Probe
1000 pF
IXYS reserves the right to change limits, test conditions, and dimensions.
5
Agilent 1147A
Current Probe
1000 pF
5 Page 
IXDF502 / IXDI502 / IXDN502www.DataSheet4U.com
Supply Bypassing, Grounding Practices And
Output Lead inductance
When designing a circuit to drive a high speed MOSFET utilizing
the IXD_502, it is very important to observe certain design criteria
in order to optimize performance of the driver. Particular attention
needs to be paid to Supply Bypassing, Grounding, and
minimizing the Output Lead Inductance.
Say, for example, we are using the IXD_502 to charge a 1500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I = C ∆V/∆t, where ∆V=25V C=1500pF &
∆t=25ns, we can determine that to charge 1500pF to 25 volts in
25ns will take a constant current of 1.5A. (In reality, the charging
current won’t be constant, and will peak somewhere around 2A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXD_502
must be able to draw this 1.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is an order of
magnitude larger than the load capacitance. Usually, this would
be achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected and should
have low inductance, low resistance and high-pulse current-
service ratings). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of the
leads between these bypass capacitors and the IXD_502 to an
absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXD_502
must be able to drain this 1.5A of current into an adequate
grounding system. There are three paths for returning current that
need to be considered: Path #1 is between the IXD_502 and its
load. Path #2 is between the IXD_502 and its power supply. Path
#3 is between the IXD_502 and whatever logic is driving it. All three
of these paths should be as low in resistance and inductance as
possible, and thus as short as practical. In addition, every effort
should be made to keep these three ground paths distinctly
separate. Otherwise, the returning ground current from the load
may develop a voltage that would have a detrimental effect on the
logic line driving the IXD_502.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort should
be made to keep the leads between the driver and its load as short
and wide as possible. If the driver must be placed farther than 0.2”
(5mm) from the load, then the output leads should be treated as
transmission lines. In this case, a twisted-pair should be
considered, and the return line of each twisted pair should be
placed as close as possible to the ground pin of the driver, and
connected directly to the ground terminal of the load.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet IXDF502.PDF ] | |
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