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MR4010 の電気的特性と機能

MR4010のメーカーはLSI Logicです、この部品の機能は「Superscalar Microprocessor」です。


製品の詳細 ( Datasheet PDF )

部品番号 MR4010
部品説明 Superscalar Microprocessor
メーカ LSI Logic
ロゴ LSI Logic ロゴ 




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MR4010 Datasheet, MR4010 PDF,ピン配置, 機能
MiniRISC™ MR4010
Superscalar
Microprocessor
Reference Device
www.DataSheet4U.com
Contents
1 MR4010 Features
2 MR4010 Functional Blocks
2.1 CW4010 Shell
2.2 Synchronous DRAM Controller (DRAMC)
2.3 SCbus to Local I/O Bus (Lbus) Controller (SCLC)
2.4 PLL Clock Circuit
3 MR4010 Programming Model
4 Signal Descriptions
4.1 SCbus Interface
4.2 External Buffering for SCbus Signals
4.3 CW4010 Shell Interface
4.4 Mbus Interface
4.5 Lbus Interface
4.6 Phase-Locked Loop (PLL) Clock Signals
4.6 Test Signals
4.7 CW4010 Core Monitor Signals
5 PLL Circuit
6 System Configuration
6.1 CW4010 CCC Register
6.2 Lbus Controller Registers
7 MR4010 Memory Map
8 CW4010 Instruction Set Summary
9 DRAM Controller and Memory Bus
9.1 DRAM Types and Available DRAM Address Area
9.2 Memory Interface
9.3 Address Bit Assignment
9.4 DRAM Modes and Programmable Configurations
9.5 DRAM Refresh
9.6 DRAM Commands
9.7 Initializing the DRAM and Programming the Mode
November 1996
Copyright © 1996 by LSI Logic Corporation. All rights reserved.
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MR4010 pdf, ピン配列
Figures
www.DataSheet4U.com
1 Block Diagram of MR4010 and Evaluation Board Circuitry
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2 MR4010 Reference Device Block Diagram
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3 Block Diagram of CW4010 Shell Modules and CW4010 Core 10
4 MR4010 Buses
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5 SCbus Interface
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6 Buffering for SCAp[31:0] Address Bus
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7 Buffering for SCDp[63:0] Data Bus
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8 Buffering for SCBEn[7:0] Byte Enable
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9 Shell Interface Overview
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10 Mbus and Lbus Interface
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11 MR4010 PLL Circuit Diagram
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12 CW4010 CCC Register
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13 MR4010 Master/Slave Memory Map
43
14 MR4010 Interface with DRAM
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15 SCbus DRAM Address Bit Assignment
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16 DRAM Mode Register Format
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17 DRAM Controller Configuration Register Format
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18 DRAM Refresh Interval Timer
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19 Timing Requirements for the DRAM Initialization Sequence
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20 Single Burst Read Transaction
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21 Two Continuous Single Write Transactions
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22 Burst Write Transaction
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23 Timing Requirements for an SCbus-to-Lbus Transaction
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24 Timing Requirements for Lbus-to-SCbus Transaction
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25 SCbus Error Address and Status Register Bit Format
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26 External Vectored Interrupt Register Bit Format
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27 MR4010 PLL Clock Circuitry
90
28 Timing Requirements for the CW4010 and Lbus Clocks
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29 Exception Inputs Synchronization Circuitry
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30 Timing Requirements for Synchronization Circuit
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31 AC Timing for MR4010 Inputs and Outputs
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32 Mechanical Drawing of the 299-Pin CPGA (FT) MR4010 Device 97
MiniRISC MR4010 Superscalar Microprocessor
3


3Pages


MR4010 電子部品, 半導体
Overview
www.DataSheet4U.com
The MiniRISC MR4010 Microprocessor Reference Device is a chip
implementation of the MiniRISC CW4010 Microprocessor core and shell.
The MR4010 contains the following circuitry:
The CW4010 shell, which is an unencrypted Verilog model contain-
ing the CW4010 core, the Multiply/Divide unit, Instruction cache
(Icache), Data cache (Dcache), Memory Management Unit (MMU),
and a Writeback Buffer
A DRAM Controller (DRAMC) that controls the memory bus and an
external synchronous DRAM array
An SCbus/Lbus Converter (SCLC) that controls the Local I/O bus
and external Lbus devices
A Phase-Locked Loop (PLL) circuit that supplies clock inputs to the
other modules in the MR4010
The MR4010 uses the maximum configuration CW4010 shell. You can
disable optional modules by programming the Configuration Register in
the CW4010 core’s Coprocessor 0 (CP0). “MR4010 Functional Blocks,”
starting on page 9, provides further information about the different
elements of the MR4010.
The MR4010 is housed on an evaluation board that allows you to use
and test the microprocessor. In addition to the MR4010 Reference
Device, the board also contains the DRAM array and Lbus facilities for
plugging in devices such as a Boot-ROM, serial I/O devices, and an
external Ethernet Controller. Figure 1 provides a block diagram of the
MR4010 evaluation board circuitry.
6 MiniRISC MR4010 Superscalar Microprocessor

6 Page



ページ 合計 : 30 ページ
 
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共有リンク

Link :


部品番号部品説明メーカ
MR4010

Partial Resonance Power Supply IC Module

Shindengen
Shindengen
MR4010

Superscalar Microprocessor

LSI Logic
LSI Logic


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