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71M6534H の電気的特性と機能

71M6534HのメーカーはTERIDIAN Semiconductorです、この部品の機能は「Energy Meter IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 71M6534H
部品説明 Energy Meter IC
メーカ TERIDIAN Semiconductor
ロゴ TERIDIAN Semiconductor ロゴ 




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71M6534H Datasheet, 71M6534H PDF,ピン配置, 機能
Simplifying System IntegrationTM
GENERAL DESCRIPTION
The 71M6533 and 71M6534 are Teridian’s 3rd-generation poly-
phase metering SOCs with a 10MHz 8051-compatible MPU
core, low-power RTC, FLASH and LCD driver. Teridian’s pa-
tented Single Converter Technology® with a 22-bit delta-sigma
ADC, seven analog inputs, digital temperature compensation,
precision voltage reference and a 32-bit computation engine
(CE) supports a wide range of metering applications with very
few external components.
The 71M6533 and 71M6534 add several new features to Teri-
dian’s flagship 71M6513 poly-phase meters including an SPI in-
terface, advanced power management with <1 µA sleep cur-
rent, 4 KB shared RAM and 128 KB (71M6533/H, 71M6534) or
256 KB (71M6534H) Flash which may be programmed in the
field with new code and/or data during meter operation. Higher
processing and sampling rates and larger memory offer a po-
werful metering platform for commercial and industrial meters
with up to class 0.2 accuracy.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of meters that meet all ANSI & IEC electricity meter-
ing standards worldwide.
LIVE
NEUT
LIVE
CT/ COIL
LIVE
AMR
IR
POWER
FAULT
LOAD
NEUTRAL
POWER SUPPLY
CONVERTER
IA
VA
IB
VB
IC
VC
ID
V3P3A V3P3SYS GNDA GNDD
TERIDIAN
71M6533
71M6534
PWR MODE
CONTROL
WAKE-up
REGULATOR
VBAT
V2P5
TEMP
SENSOR
LCD DRIVER
DIO ,PULSE
VREF
SERIAL PORTS
TX
RX
RAM
COMPUTE
ENGINE
COM0..3
SEG
SEG/ DIO
RX
MOD TX
COMPARATOR
V1
V2*
FLASH
MPU
RTC
TIMERS
ICE
DIO
OSC/ PLL
XIN
XOUT
* 71M6534 only
9/24/2008
BATTERY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
www.DataSheet4U.com
71M6533/H and 71M6534/H
Energy Meter IC
DATA SHEET
November 2009
FEATURES
Accuracy < 0.1% over 2000:1 range
Exceeds IEC62053 / ANSI C12.20 standards
Seven sensor inputs with neutral current
measurement
Low-jitter Wh and VARh plus two additional
pulse test outputs (4 total, 10 kHz maximum)
with pulse count
Four-quadrant metering
Phase sequencing
Line frequency count for RTC
Digital temperature compensation
Independent 32-bit compute engine
46-64 Hz line frequency range with same
calibration. Phase compensation ( 7 )
Three battery back-up modes with wake-up
on timer or push-button:
Brownout mode (82 µA typ., 71M6533)
LCD mode (21 µA typ., DAC active)
Sleep mode (0.7 µA typ.)
Energy display during mains power failure
39 mW typical consumption @ 3.3 V, MPU
clock frequency 614 kHz
8-bit MPU (80515), 1 clock cycle per in-
struction, 10 MHz maximum, with integrated
ICE for debug
LCD driver with 4 common segment drivers:
Up to 228 (71M6533) or 300 (71M6534)
pixels
4 dedicated plus 35 (71M6533) or
48 (71M6534) multi-function DIO pins
RTC for TOU functions with clock-rate adjust
register
Hardware watchdog timer, power fail monitor
I2C/Microwire EEPROM Interface
High-speed slave SPI interface to data RAM
Two UARTs for IR and AMR, IR driver with
modulation
Flash memory with security and in-system
program update:
128 KB (71M6533/H, 71M6534)
256 KB (71M6534H)
4 KB RAM
Industrial temperature range
100-pin (71M6533/H) or 120-pin
(71M6534/H) lead free LQFP package
v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation 1

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71M6534H pdf, ピン配列
FDS_6533_6534_004
71M6533/71M653w4wDwa.DtaataSShheeete4Ut .com
2.3.3 SLEEP Mode ................................................................................................................. 57
2.4 Fault and Reset Behavior........................................................................................................ 62
2.4.1 Reset Mode.................................................................................................................... 62
2.4.2 Power Fault Circuit ........................................................................................................ 62
2.5 Wake Up Behavior ................................................................................................................... 63
2.5.1 Wake on PB ................................................................................................................... 63
2.5.2 Wake on Timer............................................................................................................... 63
2.6 Data Flow .................................................................................................................................. 64
2.7 CE/MPU Communication......................................................................................................... 64
3 Application Information.................................................................................................................... 65
3.1 Connection of Sensors (CT, Resistive Shunt) ...................................................................... 65
3.2 Distinction between 71M6533/71M6534 and 71M6533H/71M6534H Parts .......................... 65
3.3 Connecting 5 V Devices .......................................................................................................... 66
3.4 Temperature Measurement ..................................................................................................... 66
3.5 Temperature Compensation ................................................................................................... 66
3.5.1 Temperature Coefficients .............................................................................................. 66
3.5.2 Temperature Compensation for VREF .......................................................................... 67
3.5.3 System Temperature Compensation ............................................................................. 67
3.5.4 Temperature Compensation for the RTC ...................................................................... 67
3.6 Connecting LCDs ..................................................................................................................... 67
3.7 Connecting I2C EEPROMs....................................................................................................... 68
3.8 Connecting Three-Wire EEPROMs......................................................................................... 69
3.9 UART0 (TX/RX) ......................................................................................................................... 69
3.10 Optical Interface (UART1) ....................................................................................................... 70
3.11 Connecting the V1 Pin ............................................................................................................. 70
3.12 Connecting the Reset Pin ....................................................................................................... 71
3.13 Connecting the Emulator Port Pins ....................................................................................... 71
3.14 Connecting a Battery............................................................................................................... 72
3.15 Flash Programming ................................................................................................................. 72
3.16 MPU Firmware Library............................................................................................................. 73
3.17 Crystal Oscillator ..................................................................................................................... 73
3.18 Meter Calibration...................................................................................................................... 73
4 Firmware Interface ............................................................................................................................ 74
4.1 I/O RAM Map Functional Order............................................................................................. 74
4.2 I/O RAM Description Alphabetical Order............................................................................ 78
4.3 CE Interface Description ......................................................................................................... 91
4.3.1 CE Program ................................................................................................................... 91
4.3.2 CE Data Format ............................................................................................................. 91
4.3.3 Constants....................................................................................................................... 91
4.3.4 Environment................................................................................................................... 92
4.3.5 CE Calculations ............................................................................................................. 92
4.3.6 CE Front End Data (Raw Data) ..................................................................................... 92
4.3.7 CE Status and Control ................................................................................................... 93
4.3.8 CE Transfer Variables ................................................................................................... 95
4.3.9 Other Measurement and Control Parameters ............................................................... 97
4.3.10 CE Calibration Parameters ............................................................................................ 99
4.3.11 CE Flow Diagrams......................................................................................................... 99
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
3


3Pages


71M6534H 電子部品, 半導体
71M6533/71M6534 Data Sheet
FDS_653w3w_w6.D5a3ta4S_he0e0t44U.com
Tables
Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV = 7) ................... 11
Table 2: ADC Resolution............................................................................................................................. 11
Table 3: ADC RAM Locations ..................................................................................................................... 12
Table 4: XRAM Locations for ADC Results ................................................................................................ 15
Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 15
Table 6: CKMPU Clock Frequencies .......................................................................................................... 19
Table 7: Memory Map ................................................................................................................................. 20
Table 8: Internal Data Memory Map ........................................................................................................... 21
Table 9: Special Function Register Map ..................................................................................................... 22
Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................... 22
Table 11: PSW Bit Functions (SFR 0xD0) ................................................................................................... 23
Table 12: Port Registers ............................................................................................................................. 24
Table 13: Stretch Memory Cycle Width ...................................................................................................... 25
Table 14: 71M6533/71M6534 Specific SFRs ............................................................................................. 25
Table 15: Baud Rate Generation ................................................................................................................ 27
Table 16: UART Modes............................................................................................................................... 27
Table 17: The S0CON (UART0) Register (SFR 0x98)................................................................................. 28
Table 18: The S1CON (UART1) Register (SFR 0x9B) ................................................................................ 28
Table 19: PCON Register Bit Description (SFR 0x87) ............................................................................... 28
Table 20: Timers/Counters Mode Description ............................................................................................ 29
Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 29
Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................ 29
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 30
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 31
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 32
Table 28: The T2CON Bit Functions (SFR 0xC8)....................................................................................... 32
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 32
Table 30: External MPU Interrupts.............................................................................................................. 33
Table 31: Interrupt Enable and Flag Bits .................................................................................................... 33
Table 32: Interrupt Priority Level Groups .................................................................................................... 34
Table 33: Interrupt Priority Levels ............................................................................................................... 34
Table 34: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 34
Table 35: Interrupt Polling Sequence.......................................................................................................... 35
Table 36: Interrupt Vectors.......................................................................................................................... 35
Table 37: Clock System Summary.............................................................................................................. 37
Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................ 41
Table 39: Data/Direction Registers and Internal Resources for DIO Pin Groups ....................................... 43
Table 40: Selectable Resources using the DIO_Rn Bits ............................................................................. 45
Table 41: EECTRL Bits for 2-pin Interface................................................................................................... 47
Table 42: EECTRL Bits for the 3-wire Interface ........................................................................................... 47
Table 43: SPI Command Description.......................................................................................................... 50
Table 44: TMUX[4:0] Selections ................................................................................................................. 52
Table 45: Available Circuit Functions.......................................................................................................... 56
Table 46: I/O RAM Map Functional Order ............................................................................................... 74
Table 47: I/O RAM Description Alphabetical (by Bit Name) .................................................................... 78
Table 48: CE EQU Equations and Element Input Mapping ........................................................................ 92
Table 49: CE Raw Data Access Locations ................................................................................................. 92
Table 50: CESTATUS Register..................................................................................................................... 93
Table 51: CESTATUS Bit Definitions ............................................................................................................ 93
Table 52: CECONFIG Register.................................................................................................................... 93
Table 53: CECONFIG Bit Definitions ........................................................................................................... 94
Table 54: Sag Threshold and Gain Adjust Control ..................................................................................... 95
Table 55: CE Transfer Variables................................................................................................................. 95
6
© 2007-2009 TERIDIAN Semiconductor Corporation
v1.1

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部品番号部品説明メーカ
71M6534

Energy Meter IC

TERIDIAN Semiconductor
TERIDIAN Semiconductor
71M6534H

Energy Meter IC

TERIDIAN Semiconductor
TERIDIAN Semiconductor


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