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71M6532D の電気的特性と機能

71M6532DのメーカーはTERIDIAN Semiconductorです、この部品の機能は「Energy Meter IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 71M6532D
部品説明 Energy Meter IC
メーカ TERIDIAN Semiconductor
ロゴ TERIDIAN Semiconductor ロゴ 




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71M6532D Datasheet, 71M6532D PDF,ピン配置, 機能
Simplifying System IntegrationTM
www.DataSheet4U.com
71M6531D/F, 71M6532D/F
Energy Meter IC
DATA SHEET
GENERAL DESCRIPTION
The Teridian 71M6531D/F and 71M6532D/F are highly
integrated SOCs with an MPU core, RTC, FLASH and LCD
driver. Teridian’s patented Single Converter Technology®
with a 22-bit delta-sigma ADC, four analog inputs, digital
temperature compensation, precision voltage reference, battery
voltage monitor and 32-bit computation engine (CE) supports
a wide range of residential metering applications with very few
low-cost external components.
A 32-kHz crystal time base for the entire system and internal
battery backup support for RAM and RTC further reduce system
cost. The IC supports 2-wire, and 3-wire single-phase and
dual-phase residential metering along with tamper-detection
mechanisms. The 71M6531D/F offers single-ended inputs for
two current channels and two single-ended voltage inputs.
The 71M6532D/F has two differential current inputs and three
single-ended voltage inputs.
Maximum design flexibility is provided by multiple UARTs, I2C,
μWire, up to 21 DIO pins and in-system programmable FLASH
memory, which can be updated with data or application code
in operation.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of TOU, AMR and Prepay meters that comply with
worldwide electricity metering standards.
CT/SHUNT
A
NEUTRAL
CT
B
LOAD
LOAD
POWER SUPPLY
AMR
RX/DIO1
IR TX/DIO2
POWER
FAULT
32 kHz
ADC
IAP*
IAN*
VA
IBP*
IBN*
VB
V3.3A
V3.3
SYS
GNDA GNDD
PWR MODE
TERIDIAN CONTROL
71M6531 WAKE-UP
71M6532 REGULATOR
VBAT
V2.5
VOLTAGE REF
VREF
VBIAS
TEMP
SENSOR
RAM
LCD & DIO
COM0..3
LCD SEG
SERIAL PORTS
TX
RX
SENSE
DRIVE/MOD
COMPARATOR
V1
OSC/PLL
XIN
XOUT
FLASH
MEMORY
COMPUTE
ENGINE
MPU
TIMERS
RTC
ICE I/F
SEG/DIO
SPI
ICE_E
* Differential pins only on 6532D/F
02/18/2009
BATTERY
88. 88. 8888
I2C or µWire
EEPROM
TEST PULSES
SPI HOST
V3P3D
GNDD
June 2010
FEATURES
Wh accuracy < 0.1% over 2000:1 current
range
Exceeds IEC62053/ANSI C12.20 standards
Four sensor inputs
Low-jitter Wh and VARh plus two additional
pulse test outputs (4 total, 10 kHz maximum)
with pulse count
Four-quadrant metering
Tamper detection (Neutral current with CT,
Rogowski or shunt, magnetic tamper input)
Line frequency count for RTC
Digital temperature compensation
Sag detection for phase A and B
Independent 32-bit compute engine
46-64 Hz line frequency range with same
calibration. Phase compensation (± 7°)
Three battery modes with wake-up on timer
or push-button:
Brownout mode (52 µA typ.)
LCD mode (21 µA typ., DAC active)
Sleep mode (0.7 µA typ.)
Energy display during mains power failure
39 mW typical consumption @ 3.3 V, MPU
clock frequency 614 kHz
22-bit delta-sigma ADC with 3360 Hz or
2520 Hz sample rate
8-bit MPU (80515),1 clock cycle per instruction,
10 MHz maximum, with integrated ICE for
debug
RTC for TOU functions with clock-rate adjust
register
Hardware watchdog timer, power fail monitor
LCD driver with 4 common segment drivers:
Up to 156 (71M6531D/F) or 268 pixels
(71M6532D/F)
Up to 22 (71M6531D/F) or 43 (71M6532D/F)
general-purpose I/O pins. Digital I/O pins
compatible with 5 V inputs
32 kHz time base
High-speed slave SPI interface to data RAM
Two UARTs for IR and AMR, IR driver with
modulation
FLASH memory with security and in-system
program update:
128 KB (71M6531D/32D)
256 KB (71M6531F/32F)
4 KB MPU XRAM
Industrial temperature range
68-pin QFN package for 71M6531D/F pin-
compatible with 71M6521, 100-pin LQFP
package for 71M6532D/F, lead free
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 1

1 Page





71M6532D pdf, ピン配列
FDS 6531/6532 005
Data Sheet 71M6531D/F-w7w1wM.D6a5ta3S2heDet/4FU.com
2 Functional Description ..................................................................................................................... 54
2.1 Theory of Operation ................................................................................................................... 54
2.2 System Timing Summary........................................................................................................... 55
2.3 Battery Modes............................................................................................................................ 56
2.3.1 BROWNOUT Mode ....................................................................................................... 57
2.3.2 LCD Mode...................................................................................................................... 58
2.3.3 SLEEP Mode ................................................................................................................. 58
2.4 Fault and Reset Behavior .......................................................................................................... 60
2.4.1 Reset Mode.................................................................................................................... 60
2.4.2 Power Fault Circuit ........................................................................................................ 60
2.5 Wake-Up Behavior..................................................................................................................... 61
2.5.1 Wake on PB ................................................................................................................... 61
2.5.2 Wake on Timer............................................................................................................... 61
2.6 Data Flow ................................................................................................................................... 61
2.7 CE/MPU Communication ........................................................................................................... 62
3 Application Information.................................................................................................................... 63
3.1 Connection of Sensors............................................................................................................... 63
3.2 Connecting 5-V Devices ............................................................................................................ 63
3.3 Temperature Measurement ....................................................................................................... 64
3.4 Temperature Compensation ...................................................................................................... 64
3.4.1 Temperature Coefficients: ............................................................................................. 64
3.4.2 Temperature Compensation for VREF .......................................................................... 65
3.4.3 System Temperature Compensation............................................................................. 65
3.4.4 Temperature Compensation for the RTC ...................................................................... 65
3.5 Connecting LCDs....................................................................................................................... 66
3.6 Connecting I2C EEPROMs ........................................................................................................ 66
3.7 Connecting Three-Wire EEPROMs ........................................................................................... 67
3.8 UART0 (TX/RX) ......................................................................................................................... 67
3.9 Optical Interface (UART1).......................................................................................................... 67
3.10 Connecting the V1 Pin ............................................................................................................... 68
3.11 Connecting the Reset Pin .......................................................................................................... 69
3.12 Connecting the Emulator Port Pins............................................................................................ 69
3.13 Connecting a Battery ................................................................................................................. 69
3.14 Flash Programming.................................................................................................................... 70
3.15 MPU Firmware ........................................................................................................................... 70
3.16 Crystal Oscillator........................................................................................................................ 70
3.17 Meter Calibration........................................................................................................................ 71
4 Firmware Interface ............................................................................................................................ 72
4.1 I/O RAM and SFR Map – Functional Order ............................................................................... 72
4.2 I/O RAM Description – Alphabetical Order ................................................................................ 77
4.3 CE Interface Description ............................................................................................................ 88
4.3.1 CE Program ................................................................................................................... 88
4.3.2 CE Data Format ............................................................................................................. 88
4.3.3 Constants....................................................................................................................... 88
4.3.4 Environment................................................................................................................... 88
4.3.5 CE Calculations ............................................................................................................. 89
4.3.6 CE Status and Control ................................................................................................... 89
4.3.7 CE Transfer Variables ................................................................................................... 92
4.3.8 Pulse Generation ........................................................................................................... 93
4.3.9 CE Calibration Parameters ............................................................................................ 94
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation
3


3Pages


71M6532D 電子部品, 半導体
Data Sheet 71M6531D/F-71M6532D/F
FDS 65w3w1w/6.D5at3a2She0e0t45U.com
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 11
Table 2: ADC Resolution............................................................................................................................. 12
Table 3: ADC RAM Locations ..................................................................................................................... 12
Table 4: XRAM Locations for ADC Results ................................................................................................ 15
Table 5: Meter Equations ............................................................................................................................ 16
Table 6: CKMPU Clock Frequencies .......................................................................................................... 19
Table 7: Memory Map ................................................................................................................................. 20
Table 8: Internal Data Memory Map ........................................................................................................... 21
Table 9: Special Function Register Map ..................................................................................................... 21
Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................... 22
Table 11: PSW Bit Functions (SFR 0xD0) ..................................................................................................... 23
Table 12: Port Registers ............................................................................................................................. 24
Table 13: Stretch Memory Cycle Width ...................................................................................................... 24
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs........................................................................... 24
Table 15: Baud Rate Generation ................................................................................................................ 26
Table 16: UART Modes............................................................................................................................... 26
Table 17: The S0CON (UART0) Register (SFR 0x98)................................................................................. 27
Table 18: The S1CON (UART1) register (SFR 0x9B).................................................................................. 27
Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................ 28
Table 20: Timers/Counters Mode Description ............................................................................................ 28
Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 29
Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................ 29
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 29
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 30
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 31
Table 28: The T2CON Bit Functions (SFR 0xC8)........................................................................................ 31
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 31
Table 30: External MPU Interrupts.............................................................................................................. 32
Table 31: Interrupt Enable and Flag Bits .................................................................................................... 32
Table 32: Interrupt Priority Level Groups .................................................................................................... 33
Table 33: Interrupt Priority Levels ............................................................................................................... 33
Table 34: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 34
Table 35: Interrupt Polling Sequence.......................................................................................................... 34
Table 36: Interrupt Vectors.......................................................................................................................... 34
Table 37: Clock System Summary.............................................................................................................. 36
Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................ 40
Table 39: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6531D/F) ......................... 42
Table 40: Data/Direction Registers and Internal Resources for DIO 17-29 (71M6531D/F) ....................... 42
Table 41: Data/Direction Registers and Internal Resources for DIO 43-46 (71M6531D/F) ....................... 42
Table 42: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6532D/F) ......................... 43
Table 43: Data/Direction Registers and Internal Resources for DIO 16-30 (71M6532D/F) ....................... 43
Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F) ....................... 44
Table 45: DIO_DIR Control Bit .................................................................................................................... 44
Table 46: Selectable Control using DIO_DIR Bits ......................................................................................... 44
Table 47: EECTRL Bits for 2-pin Interface................................................................................................... 47
Table 48: EECTRL Bits for the 3-Wire Interface .......................................................................................... 48
Table 49: SPI Command Description.......................................................................................................... 50
Table 50: I/O RAM Registers Accessible via SPI ....................................................................................... 50
Table 51: TMUX[4:0] Selections ................................................................................................................. 53
Table 52: Available Circuit Functions.......................................................................................................... 57
6
© 2005-2010 TERIDIAN Semiconductor Corporation
v1.3

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部品番号部品説明メーカ
71M6532D

Energy Meter IC

TERIDIAN Semiconductor
TERIDIAN Semiconductor
71M6532F

Energy Meter IC

TERIDIAN Semiconductor
TERIDIAN Semiconductor


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